AM29DL400BB-120EC AMD [Advanced Micro Devices], AM29DL400BB-120EC Datasheet - Page 8

• Manufacturer Part Number: AM29DL400BB-120EC
• Description: 4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is a latch used to store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Legend:
L = Logic Low = V
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = V
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0-15 are active and controlled by CE#
and OE# .
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE# should
remain at V
device outputs array data in words or bytes.
8
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
Sector Unprotect (Note 2)
Temporary Sector Unprotect
Protection/Unprotection” section.
Operation
IH
. The BYTE# pin determines whether the
IL
, H = Logic High = V
V
0.3 V
Table 1. Am29DL400B Device Bus Operations
CE#
CC
L
L
L
X
L
L
X
IL
. CE# is the power
IH
, V
OE# WE# RESET#
H
X
H
X
H
H
X
ID
L
= 12.0 0.5 V, X = Don’t Care, A
P R E L I M I N A R Y
H
X
H
X
X
L
L
L
IH
), A17:A-1 in byte mode (BYTE# = V
Am29DL400B
V
0.3 V
V
V
V
CC
H
H
H
L
ID
ID
ID
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. Table 1 lists the device bus operations, the
inputs and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Sector Address,
Sector Address,
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs pro-
duce valid data on the device data outputs. Each bank
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read-Only Operations table for timing spec-
ifications and to Figure 13 for the timing diagram. I
in the DC Characteristics table represents the active
current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
A6 = H, A1 = H,
A6 = L, A1 = H,
Addresses
(Note 1)
A0 = L
A0 = L
A
A
A
X
X
X
IN
IN
IN
IN
= Address In, D
High-Z
High-Z
High-Z
DQ0–
D
DQ7
D
D
D
D
OUT
IN
IN
IN
IN
IL
).
BYTE#
High-Z
High-Z
High-Z
D
= V
D
D
IN
OUT
X
X
IN
IN
IH
= Data In, D
DQ8–DQ14 = High-Z,
DQ8–DQ15
DQ15 = A-1
BYTE#
OUT
High-Z
High-Z
High-Z
High-Z
= V
X
X
IL
= Data Out
CC1