EVAL-AD7324CB AD [Analog Devices], EVAL-AD7324CB Datasheet - Page 19

• Manufacturer Part Number: EVAL-AD7324CB
• Description: 4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

TYPICAL CONNECTION DIAGRAM
Figure 32 shows a typical connection diagram for the AD7324.
In this configuration, the AGND pin is connected to the analog
ground plane of the system, and the DGND pin is connected to
the digital ground plane of the system. The analog inputs on the
AD7324 can be configured to operate in single-ended, true
differential, or pseudo differential mode. The AD7324 can operate
with either an internal or external reference. In Figure 32, the
AD7324 is configured to operate with the internal 2.5 V reference.
A 680 nF decoupling capacitor is required when operating with
the internal reference.
The V
5 V supply voltage. The V
high voltage analog input structures. The voltage on these pins
must be equal to or greater than the highest analog input range
selected on the analog input channels (see
pin is connected to the supply voltage of the microprocessor.
The voltage applied to the V
the serial interface. V
+15V
–15V
ANALOG INPUT
Single-Ended Inputs
The AD7324 has a total of four analog inputs when operating in
single-ended mode. Each analog input can be independently
programmed to one of the four analog input ranges. In applications
where the signal source is high impedance, it is recommended
to buffer the signal before applying it to the ADC analog inputs.
Figure 33 shows the configuration of the AD7324 in single-
ended mode.
ANALOG INPUTS
±10V, ±5V, ±2.5V
0V TO +10V
CC
680nF
pin can be connected to either a 3 V supply voltage or a
0.1µF
0.1µF
+
+
Figure 32. Typical Connection Diagram
10µF
10µF
V
V
V
V
REFIN/OUT
IN
IN
IN
IN
0
1
2
3
V
DD
DRIVE
V
1
AD7324
SS
1
MINIMUM V
DEPEND ON THE HIGHEST ANALOG INPUT
RANGE SELECTED.
1
DD
can be set to 3 V or 5 V.
DRIVE
and V
AGND
V
CC
V
DGND
DOUT
SCLK
DRIVE
DD
DIN
10µF
CS
input controls the voltage of
AND V
SS
are the dual supplies for the
10µF
+
SS
0.1µF
SUPPLY VOLTAGES
+
Table 6). The V
0.1µF
INTERFACE
SERIAL
+3V SUPPLY
V
CC
µC/µP
+2.7V TO +5.25V
DRIVE
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True Differential Mode
The AD7324 can have a total of two true differential analog
input pairs. Differential signals have some benefits over single-
ended signals, including better noise immunity based on the
device’s common-mode rejection and improvements in
distortion performance.
the true differential analog inputs of the AD7324.
The amplitude of the differential signal is the difference
between the signals applied to the V
each differential pair (V
be simultaneously driven by two signals of equal amplitude,
dependent on the input range selected, that are 180° out of
phase. Assuming the ±4 × V
differential signal is −20 V to +20 V p-p (2 × 4 × V
regardless of the common mode.
The common mode is the average of the two signals
and is therefore the voltage on which the two input signals
are centered.
This voltage is set up externally, and its range varies with
reference voltage. As the reference voltage increases, the
common-mode range decreases. When driving the differential
inputs with an amplifier, the actual common mode range is
determined by the amplifier’s output swing. If the differential
inputs are not driven from an amplifier, the common-mode
range is determined by the supply voltage on the V
and the V
When a conversion takes place, the common mode is rejected,
resulting in a noise-free signal of amplitude −2 × (4 × V
+2 × (4 × V
(VIN+ + VIN−)/2
AGND
Figure 33. Single-Ended Mode Typical Connection Diagram
SS
REF
supply pin.
) corresponding to Digital Codes −4096 to +4095.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 34. True Differential Inputs
1
ADDITIONAL PINS OMITTED FOR CLARITY.
IN
Figure 34 defines the configuration of
+ − V
V+
V–
REF
V
V
IN
mode, the amplitude of the
IN
IN
−). V
+
–
AD7324
IN
+ and V
IN
V
+ and V
IN
+
AD7324
1
IN
− pins in
V
V
IN
DD
SS
− should
1
REF
DD
V
AD7324
5V
REF
CC
),
supply pin
) to