EVAL-AD7324CB AD [Analog Devices], EVAL-AD7324CB Datasheet - Page 7

• Manufacturer Part Number: EVAL-AD7324CB
• Description: 4-Channel, Software-Selectable, True Bipolar Input, 12-Bit Plus Sign ADC
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
V
T
Table 3.
Parameter
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
SCLK
CONVERT
QUIET
1
2
3
4
5
6
7
8
9
10
POWER-UP
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
When using V
50:50.
A
2
DD
= T
= 12 V to 16.5 V, V
MAX
to T
CC
V
50
14
16 × t
75
12
25
45
26
57
0.4 × t
0.4 × t
13
40
10
4
2
750
500
25
= 4.75 V to 5.25 V and the 0 V to 10 V unipolar range, running at 1 MSPS throughput rate with t
MIN
CC
DOUT
SCLK
DIN
. Timing specifications apply with a 32 pF load, unless otherwise noted.
< 4.75 V
CS
SCLK
THREE-
SCLK
SCLK
STATE
SS
Limit at T
= −12 V to −16.5 V, V
WRITE
ZERO
t
2
1
V
50
20
16 × t
60
5
20
35
14
43
0.4 × t
0.4 × t
8
22
9
4
2
750
500
25
2 IDENTIFICATION BITS
ADD1
t
CC
3
t
= 4.75 V to 5.25 V
SEL1
MIN
REG
9
SCLK
SCLK
SCLK
, T
2
ADD0
MAX
SEL2
REG
3
SIGN
CC
MSB
= 2.7 V to 5.25 V, V
4
Figure 2. Serial Interface Timing Diagram
DB11
t
t
6
Unit
kHz min
MHz max
ns max
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns min
ns min
ns max
μs max
μs typ
4
t
CONVERT
t
10
5
t
DB10
7
Rev. 0 | Page 7 of 36
Description
V
t
Minimum time between end of serial read and next falling edge of CS
Minimum CS pulse width
CS to SCLK setup time; bipolar input ranges (±10 V, ±5 V, ±2.5 V)
Unipolar input range (0 V to 10 V)
Delay from CS until DOUT three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to DOUT high impedance
SCLK falling edge to DOUT high impedance
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
Power up from autostandby
Power up from full shutdown/autoshutdown mode, internal reference
Power up from full shutdown/autoshutdown mode, external reference
SCLK
DRIVE
DRIVE
13
= 1/f
≤ V
= 2.7 V to 5.25, V
DB2
SCLK
CC
14
t
5
DB1
LSB
15
DB0
1
DON’T
CARE
2
REF
at 20 ns, the mark space ratio needs to be limited to
16
= 2.5 V to 3.0 V Internal/External,
THREE-STATE
t
8
DRIVE
t
) and timed from a voltage level of 1.6 V.
QUIET
t
1
AD7324