EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 14

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

THEORY OF OPERATION
The
output audio amplifier. The
and produces the PDM differential switching outputs using the
internal power stage. The part has built in protection for over-
temperature as well as overcurrent conditions. The
also has built in soft turn on and soft turn off for pop-and-click
suppression. The part has programmable register control via the
I
POWER SUPPLIES
The
Descriptions of each of these supplies follow.
PVDD
The PVDD pin supplies power to the full bridge power stage
of a MOSFET and its associated drive, control, and protection
circuitry. PVDD can operate from 2.5 V to 5.5 V and must be
present to obtain audio output. Lowering the supply PVDD
results in lower output power and, correspondingly, lower
power consumption but does not degrade audio performance.
DVDD
The DVDD pin provides power to the digital logic circuitry and
determines the input trip points. DVDD can operate from 1.62 V
to 3.6 V and must be present to obtain audio output. Lowering
the supply voltage of DVDD results in lower power consump-
tion but does not affect audio performance.
POWER-DOWN MODES
The
be used to set the IC to its lowest power state, with all blocks
disabled. This hardware shutdown mode is enabled when the
SD pin is pulled low.
When the hardware shutdown is removed, the IC begins in
software power-down mode, where all blocks except for the
I
S_RST (Bit 7 of Register 0x00). In addition to the software
power-down, the software master mute is enabled at the initial
state of the amplifier; therefore, no audio is output until Bit 0 of
Register 0x07 is cleared.
The left and right channels can be independently shut down
by setting setting L_PWDN and R_PWDN (Bit 1 and Bit 2,
respectively, in Register 0x09). Disabling a channel shuts down
the channel specific digital processing, DAC, Class-D modulator,
and power stage.
The
is enabled by default. This feature can be disabled by clearing
APWDN_EN (Bit 0 in Register 0x09). When active, this feature
SSM2518
2
2
C port.
C interface are disabled. To fully power up the amplifier, clear
SSM2518
SSM2518
SSM2518
SSM2518
is fully integrated 2-channel digital input, Class-D
requires two power supplies: PVDD and DVDD.
offers a hardware shutdown pin, SD , which can
also contains a smart power-down feature, which
SSM2518
receives digital audio input
SSM2518
Rev. A | Page 14 of 48
monitors the incoming digital audio signal. If this is zero for
1024 consecutive samples, regardless of sample rate, it puts the
IC in the smart power-down state wherein all blocks, except the
I
nonzero input is received on the I
this state and resumes normal operation.
POWER-ON RESET/VOLTAGE SUPERVISOR
The
supervisor circuit. This circuit provides an internal reset to all
circuitry whenever PVDD or DVDD is substantially below the
nominal operating threshold. This circuit simplifies supply
sequencing during initial power-on.
The circuit also monitors the power supplies to the SSM2518. If
the supply voltages fall below the nominal operating threshold,
this circuit stops the output and issues a reset. This ensures that
no damage occurs due to low voltage operation and that no pops
can occur under nearly any power removal condition.
MASTER AND BIT CLOCK
The
clock must run at a frequency between 2.048 MHz and 6.144 MHz,
depending on the input sample rate, and it must be fully synchro-
nous with the incoming audio data. This clock signal can be
derived from either the MCLK or BCLK pin, depending on the
configuration used.
If the MCLK pin is used, the internal clock is derived by either
dividing, passing through, or doubling the external clock signal
as required. The clock supplied to the MCLK pin can range from
2.048 MHz to 38.864 MHz. In this case, the external MCLK pin
signal can run at various multiples of the audio sample rate (f
The relationship between the MCLK rate and the audio sample
rate is determined by the master clock select (MCS) register setting,
Bits[4:1] in Register 0x00. Table 11 provides a summary of the
available options.
In addition, a bit clock must run at the same rate as the incoming
audio data on the SDATA pin. This clock can be supplied to the
BCLK pin, or it can be generated internally by dividing MCLK.
In this case, when BCLK_GEN (Bit 7 of Register 0x03) is set, the
logic level of the BCLK pin is used to select the audio interface
BCLK rate. Tie the BCLK pin to DVDD for 16 clock cycles per
channel; tie it to ground for 32 cycles per channel.
If the system bit clock is in the range of acceptable internal
master clock frequencies (between 2.048 MHz and 6.144 MHz),
then it can serve as both master clock and bit clock. Setting
NO_BCLK (Bit 5 of Register 0x00) routes the signal on the
2
S and I
SSM2518
SSM2518
2
C ports, are placed in a low power state. Once a single
includes an internal power-on reset and voltage
requires an internal master clock to operate. This
2
S interface, the
Data Sheet
SSM2518
leaves
S
).