EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 7

• Manufacturer Part Number: EVAL-SSM2518Z
• Description: Digital Input Stereo, 2 W, Class-D
• Manufacturer: AD [Analog Devices]

Data Sheet
DIGITAL TIMING
All timing specifications are given for the default setting (I
Table 5.
Parameter
MASTER CLOCK
SERIAL PORT
I
Digital Timing Diagrams
2
C PORT
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
t
t
SCL
MP
MP
BIL
BIH
LIS
LIH
SIS
SIH
SCLH
SCLL
SCS
SCH
DS
SCR
SCF
SDR
SDF
BFT
RIGHT-JUSTIFIED
LEFT-JUSTIFIED
I
2
C-JUSTIFIED
SDA
SCL
SDATA
SDATA
SDATA
LRCLK
MODE
MODE
MODE
BCLK
CONDITION
t
BIH
START
t
t
t
BIL
LIS
SIS
MSB
Min
74
148
40
40
10
10
10
10
0.6
1.3
0.6
0.6
100
0.6
t
SCH
t
SIH
t
t
BP
SCLL
Limit
t
SCR
t
SIS
MSB – 1
Max
136
271
400
300
300
300
300
MSB
t
t
SIH
SCF
t
SCLH
Figure 2. Serial Input Port Timing
t
2
DS
Figure 3. I
S mode) of the serial input port.
Rev. A | Page 7 of 48
Unit
ns
ns
ns
ns
ns
ns
ns
ns
kHz
μs
μs
μs
μs
ns
ns
ns
ns
ns
μs
2
C Port Timing
Description
MCLK period, 256 × f
MCLK period, 128 × f
BCLK low pulse width
BCLK high pulse width
Setup time from LRCLK or SDATA edge to BCLK rising edge
Hold time from BCLK rising edge to LRCLK or SDATA edge
SDATA setup time to BCLK rising
SDATA hold time from BCLK rising
SCL frequency
SCL high
SCL low
Setup time; relevant for repeated start condition
Hold time; after this period, the first clock is generated
Data setup time
SCL rise time
SCL fall time
SDA rise time
SDA fall time
Bus-free time (time between stop and start)
t
t
SCS
SIS
MSB
t
SIH
t
S
S
SCH
mode (MCS = b0010)
mode (MCS = b0001)
t
BFT
t
SIS
CONDITION
LSB
STOP
t
t
SIH
LIH
SSM2518