EVAL-SSM2518Z AD [Analog Devices], EVAL-SSM2518Z Datasheet - Page 44

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EVAL-SSM2518Z

Manufacturer Part Number
EVAL-SSM2518Z
Description
Digital Input Stereo, 2 W, Class-D
Manufacturer
AD [Analog Devices]
Datasheet
DRC CONTROL 7 REGISTER
Address: 0x10, Reset: 0x26, Name: DRC_Control_7
Table 29. Bit Descriptions for DRC_Control_7
Bits
[7:4]
[3:0]
SSM2518
Bit Name
HDT_NOR
HDT_NG
Settings
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Description
DRC Normal Operation Hold Time. Used to prevent the gain curve
calculation from increasing too quickly.
0 ms
0.67 ms
1.33 ms
2.67 ms
5.33 ms
10.66 ms
21.32 ms
42.64 ms
85.28 ms
170.56 ms
341.12 ms
682.24 ms
1.364 sec
Reserved
Reserved
Reserved
DRC Noise Gate Hold Time. Used to prevent the DRC from entering noise
gate too quickly.
0 ms
0.67 ms
1.33 ms
2.67 ms
5.33 ms
10.66 ms
21.32 ms
42.64 ms
85.28 ms
170.56 ms
Rev. A | Page 44 of 48
Data Sheet
Reset
0x2
0x6
Access
RW
RW

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