74ALVCH16841DGG,11 NXP Semiconductors, 74ALVCH16841DGG,11 Datasheet - Page 3

• Manufacturer Part Number: 74ALVCH16841DGG,11
• Description: IC 20BIT BUS INTRFC D 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr
• Type: D-Typer

Specifications of 74ALVCH16841DGG,11

• Logic Type: D-Type Transparent Latch
• Package / Case: 56-TSSOP
• Circuit: 10:10
• Output Type: Tri-State
• Voltage - Supply: 2.3 V ~ 3.6 V
• Independent Circuits: 2
• Delay Time - Propagation: 2.5ns
• Current - Output High, Low: 24mA, 24mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Logic Family: ALVC
• Polarity: Non-Inverting
• Input Bias Current (max): 0.2 uA
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 2.4 ns at 3.3 V
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Bits: 20
• Number Of Elements: 2
• Latch Mode: Transparent
• Technology: CMOS
• Package Type: TSSOP
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (min): 2.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74ALVCH16841DG-T; 74ALVCH16841DG-T; 935259090118

Philips Semiconductors
PIN DESCRIPTION
FUNCTION TABLE
H = High voltage level
L = Low voltage level
X = Don’t care
Z = High impedance “off” state
LOGIC SYMBOL
1998 Jul 27
55, 54, 52, 51, 49,
2, 3, 5, 6, 8, 9, 10,
42, 41, 40, 38, 37,
15, 16, 17, 19, 20,
48, 47, 45, 44, 43
36, 34, 33, 31, 30
21, 23, 24, 26, 27
20-bit bus interface D-type latch (3-State)
4, 11, 18, 25, 32,
PIN NUMBER
nOE
7, 22, 35, 50
56
29
28
H
L
L
L
12, 13, 14
39, 46, 53
1
56
28
29
1
1LE
1OE
2LE
2OE
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
55
42
15
2
INPUTS
LE
54
41
16
H
H
X
L
3
52
40
17
5
1D0 – 1D9
1Q0 – 1Q9
2D0 – 2D9
2Q0 – 2Q9
SYMBOL
51
38
19
GND
6
1OE
2OE
1LE
V
2LE
CC
Dx
49
37
20
H
L
X
X
8
48
36
21
9
47
10
34
23
Output enable inputs
(active-LOW)
Latch enable inputs
(active HIGH)
Data inputs
Data outputs
Ground (0V)
Positive supply
voltage
Output enable inputs
(active-LOW)
Latch enable inputs
(active HIGH)
Data inputs
Data outputs
45
12
33
24
FUNCTION
OUTPUT
1Q8 1Q9
2Q8 2Q9
1D8 1D9
2D8 2D9
44
13
31
26
Q
Q
SH00023
H
Z
L
0
43
14
30
27
3
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM
1OE
2OE
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1LE
2LE
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
nOE
nLE
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
1
nD
1D
3D
EN2
C1
EN4
C3
0
D
LE
74ALVCH16841
2
4
nQ
SH00151
0
Product specification
SH00152
10
12
13
14
15
16
17
19
20
21
23
24
26
27
2
3
5
6
8
9
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9