AM29LV642D AMD [Advanced Micro Devices], AM29LV642D Datasheet - Page 11

• Manufacturer Part Number: AM29LV642D
• Manufacturer: AMD [Advanced Micro Devices]

DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Legend: L = Logic Low = V
A
Notes:
1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at
2. Addresses are A21:A0. Sector addresses are A21:A15.
3. D
4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
5. All sectors are unprotected when shipped from the factory.
VersatileI/O™ (V
The VersatileI/O (V
set the voltage levels that the device generates at its
data outputs and the voltages tolerated at its data in-
puts to the same voltage level that is asserted on the
V
or 5 V system environment as required. For voltage
levels below 3 V, contact an AMD representative for
more information.
For example, a V
the 5 volt level, driving and receiving signals to and
from other 5 V devices on the same bus.
May 5, 2006 25022A2
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect (Note 4)
Sector Group Unprotect
(Note 4)
Temporary Sector Group
Unprotect
IN
IO
the same time.
Protection and Unprotection” section.
= Address In, D
pin. This allows the device to operate in 1.8 V, 3 V,
IN
or D
Operation
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
IN
I/O
IO
= Data In, D
IO
) control allows the host system to
of 4.5–5.5 volts allows for I/O at
) Control
IL
, H = Logic High = V
V
CC
(Note 1)
OUT
CE#
± 0.3 V
Table 1. Am29LV642D Device Bus Operations
X
X
L
L
L
L
L
L
= Data Out
OE#
H
H
H
H
H
X
X
X
L
IH
D A T A
, V
ID
WE#
H
X
H
X
X
L
L
L
L
= 8.5–12.5 V, V
Am29LV642D
V
RESET#
CC
S H E E T
V
V
V
± 0.3 V
H
H
H
H
L
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
ID
ID
ID
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# or CE2# and OE# pins to V
CE2# is the power control and selects the device. OE#
is the output control and gates array data to the output
pins. WE# should remain at V
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on the device address inputs produce valid
data on the device data outputs. The device remains
HH
= 11.5–12.5 V, X = Don’t Care, SA = Sector Address,
ACC
V
X
X
H
X
X
X
X
X
HH
A1 = H, A0 = L
A1 = H, A0 = L
SA, A6 = H,
Addresses
SA, A6 = L,
(Note 2)
A
A
A
A
X
X
X
IN
IN
IN
IN
IH
.
DQ0–DQ15
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
High-Z
High-Z
High-Z
IL
D
. CE# or
OUT
9