AM29LV642D AMD [Advanced Micro Devices], AM29LV642D Datasheet - Page 12

• Manufacturer Part Number: AM29LV642D
• Manufacturer: AMD [Advanced Micro Devices]

enabled for read access until the command register
contents are altered.
See “VersatileI/O™ (V
Refer to the AC Read-Only Operations table for timing
specifications and to Figure 13 for the timing diagram.
I
tive current specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# (or CE2#) to V
The device features an Unlock Bypass mode to facili-
tate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are re-
quired to program a word, instead of four. The “Word
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. Table 2 indicates the address
space that each sector occupies.
I
tive current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This function is primarily in-
tended to allow faster manufacturing throughput dur-
ing system production.
If the system asserts V
matically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
V
eration. Note that the ACC pin must not be at V
operations other than accelerated programming, or
device damage may result.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ15–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autose-
lect Command Sequence sections for more informa-
tion.
10
CC1
CC2
HH
in the DC Characteristics table represents the ac-
in the DC Characteristics table represents the ac-
from the ACC pin returns the device to normal op-
IL
, and OE# to V
IO
HH
) Control” for more information.
on this pin, the device auto-
IH
.
D A T A
HH
Am29LV642D
for
S H E E T
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#, CE2#, and RESET# pins are all held at V
V. (Note that this is a more restricted voltage range
than V
but not within V
standby mode, but the standby current will be greater.
The device requires standard access time (t
read access when the device is in either of these
standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
vices) table represents the standby current specifica-
tion.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device en-
ergy consumption. The device automatically enables
this mode when addresses remain stable for t
30 ns. The automatic sleep mode is independent of
the CE#, CE2#, WE#, and OE# control signals. Stan-
dard address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
vices) table represents the automatic sleep mode cur-
rent specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is driven low for at least a period of t
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
draws CMOS standby current (I
at V
will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
CC3
CC4
IL
in the DC Characteristics (for Two Am29LV640 de-
in the DC Characteristics (for Two Am29LV640 de-
but not within V
IH
.) If CE#, CE2#, and RESET# are held at V
CC
± 0.3 V, the device will be in the
SS
± 0.3 V, the standby current
CC4
SS
). If RESET# is held
25022A2 May 5, 2006
± 0.3 V, the device
CC
CE
RP
ACC
± 0.3
, the
) for
IH
+
,