AM29SL160C AMD [Advanced Micro Devices], AM29SL160C Datasheet - Page 20

• Manufacturer Part Number: AM29SL160C
• Description: 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

Secured Silicon (SecSi) Sector Flash
Memory Region
The Secured Silicon (SecSi) Sector is a flash memory
region that enables permanent part identification
through an Electronic Serial Number (ESN). The SecSi
Sector in this device is 256 bytes in length. The device
contains a SecSi Sector indicator bit that allows the
system to determine whether or not the SecSi Sector
was factory locked. This indicator bit is permanently set
at the factory and cannot be changed, which prevents
a factory-locked part from being cloned.
AMD offers this device only with the SecSi Sector
factory serialized and locked. The first sixteen bytes of
the SecSi Sector contain a random ESN. To utilize the
remainder SecSi Sector space, customers must
provide their code to AMD through AMD’s Express
Flash service. The factory will program and perma-
nently protect the SecSi Sector (in addition to
programming and protecting the remainder of the
device as required).
The system can read the SecSi Sector by writing the
Enter SecSi Sector command sequence (see
SecSi Sector/Exit SecSi Sector Command Sequence”
on page
the SecSi Sector.
20
Notes:
1. All protected sectors unprotected. (If WP#/ACC = V
2. All previously protected sectors are protected once
Figure 2. Temporary Sector Unprotect Operation
the outermost sectors remain protected)
again.
24).
Table 7, on page 20
Unprotect Completed
Program Operations
Temporary Sector
Perform Erase or
RESET# = V
RESET# = V
(Note 1)
(Note 2)
START
shows the layout for
ID
IH
“Enter
Am29SL160C
IL
,
The device continues to read from the SecSi Sector
until the system issues the Exit SecSi Sector command
sequence, or until power is removed from the device.
On power-up, or following a hardware reset, the device
reverts to sending commands to the boot sectors.
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to
page 28
lowing hardware data protection measures prevent
accidental erasure or programming, which might other-
wise be caused by spurious system level signals during
V
system noise.
Low V
When V
any write cycles. This protects data during V
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
is greater than V
proper signals to the control pins to prevent uninten-
tional writes when V
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
16-byte random ESN
User-defined code or
factory erased (all 1s)
CC
IL
, CE# = V
Description
power-up and power-down transitions, or from
CC
CC
Table 7. SecSi Sector Addresses
for command definitions). In addition, the fol-
Write Inhibit
is less than V
IH
or WE# = V
IL
LKO
and OE# = V
CC
. The system must provide the
is greater than V
LKO
Word Mode
08–7Fh
00–07h
, the device does not accept
(x16)
IH
. To initiate a write cycle,
Address Range
IH
during power up, the
November 1, 2004
Byte Mode (x8)
LKO
Table 12, on
010–0FFh
000–00Fh
.
CC
CC