AM29SL160C AMD [Advanced Micro Devices], AM29SL160C Datasheet - Page 29

• Manufacturer Part Number: AM29SL160C
• Description: 16 Megabit CMOS 1.8 Volt-only Super Low Voltage Flash Memory
• Manufacturer: AMD [Advanced Micro Devices]

WRITE OPERATION STATUS
The device provides several bits to determine the
status of a program or erase operation: DQ2, DQ3,
DQ5, DQ6, DQ7, and RY/BY#.
and the following subsections describe the functions of
these bits. DQ7 and DQ6 each offer a method for deter-
mining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/BY#, to determine
whether an embedded program or erase operation is in
progress or is completed.
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host
system whether an Embedded Algorithm is in progress
or completed, or whether the device is in Erase Sus-
pend. Data# Polling is valid after the rising edge of the
final WE# pulse in the program or erase command
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status
information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
When the system detects DQ7 changes from the com-
plement to true data, it can read valid data at DQ7–
DQ0 on the following read cycles. This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low.
November 1, 2004
Table 13, on page 32
Figure 19, on
Am29SL160C
page
Algorithms), in the “AC Characteristics” section illus-
trates this.
Table 13, on page 32
Polling on DQ7.
Polling algorithm.
Notes:
1. VA = Valid address for programming. During a sector
2. DQ7 should be rechecked even if DQ5 = “1” because
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
DQ7 may change simultaneously with DQ5.
No
43, Data# Polling Timings (During Embedded
Figure 5. Data# Polling Algorithm
Read DQ7–DQ0
Read DQ7–DQ0
DQ7 = Data?
DQ7 = Data?
Addr = VA
Addr = VA
DQ5 = 1?
START
Figure 5, on page 29
FAIL
No
Yes
No
shows the outputs for Data#
Yes
Yes
shows the Data#
PASS
29