K9F2808U0A Samsung semiconductor, K9F2808U0A Datasheet - Page 3

• Manufacturer Part Number: K9F2808U0A
• Description: 16M x 8 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

K9F2808U0A-YCB0, K9F2808U0A-YIB0
Figure 2. ARRAY ORGANIZATION
Figure 1. FUNCTIONAL BLOCK DIAGRAM
V
V
(=1024 Blocks)
CC
32K Pages
SS
NOTE : Column Address : Starting Address of the Register.
2nd Cycle
CE
RE
WE
3rd Cycle
1st Cycle
Command
A
A
00h Command(Read) : Defines the starting address of the 1st half of the register.
01h Command(Read) : Defines the starting address of the 2nd half of the register.
* A
* L must be set to "Low".
9
0
- A
8
- A
is set to "Low" or "High" by the 00h or 01h Command.
1st half Page Register
(=256 Bytes)
23
7
I/O 0
A
A
A
17
512B Byte
0
9
& High Voltage
Page Register
Control Logic
CLE ALE
512 Byte
Command
X-Buffers
Latches
& Decoders
Y-Buffers
Latches
& Decoders
Generator
Register
I/O 1
A
A
A
10
18
1
2nd half Page Register
(=256 Bytes)
A
8
WP
I/O 2
A
A
A
11
19
2
16 Byte
16 Byte
I/O 3
A
A
A
12
20
3
3
I/O 4
A
A
A
13
21
I/O 0 ~ I/O 7
4
Global Buffers
(512 + 16)Byte x 32768
Page Register & S/A
I/O Buffers & Latches
I/O 5
A
A
A
128M + 4M Bit
NAND Flash
14
22
5
8 bit
Y-Gating
ARRAY
1 Page = 528 Byte
1 Block = 528 Bytes x 32 Pages
1 Device = 528Byte x 32Pages x 1024 Blocks
1 Block =32 Pages
= (16K + 512) Byte
I/O 6
A
A
A
15
23
6
= (16K + 512) Byte
= 132 Mbits
I/O 7
A
A
*L
FLASH MEMORY
16
7
Output
Driver
Column Address
Row Address
(Page Address)
V
V
CC
SS
I/0 0
I/0 7