K9F2808U0C-DCB0 Samsung semiconductor, K9F2808U0C-DCB0 Datasheet

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Document Title 16M x 8 Bit , Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 1.0 TBGA PKG Dimension Change 48-Ball, 6.0mm x 8.5mm --> 63-Ball, 9.0mm x 11.0mm 2.0 1.A3 Pin assignment of TBGA Package is changed.(Page 4) (before) NC --> (after) Vss 2. Add the ,tf & ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 16M x 8 Bit / Bit NAND Flash Memory PRODUCT LIST Part Number K9F2808Q0C-D,H K9F2816Q0C-D,H K9F2808U0C-Y,P K9F2808U0C-D,H K9F2808U0C-V,F K9F2816U0C-Y,P K9F2816U0C-D,H FEATURES Voltage Supply - 1.8V device(K9F28XXQ0C) : 1.7~1.95V - 3.3V device(K9F28XXU0C) : 2.7 ~ 3.6 V Organization - Memory Cell Array - X8 device(K9F2808X0C) : (16M + 512K)bit x 8bit - X16 device(K9F2816X0C) : (8M + 256K)bit x 16bit ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 PIN CONFIGURATION (TSOP1) X16 X8 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C GND GND R/B R N.C N.C N.C N.C Vcc Vcc Vss Vss N.C N.C N.C N.C CLE CLE ALE ALE N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8 0.45~0.75 0.018~0.030 K9F2808U0C-VCB0,VIB0 ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 PIN CONFIGURATION (TBGA /WP ALE Vss /CE NC /RE CLE I/ I/O1 NC VccQ I/O5 Vss I/O2 I/O3 I/ (Top View) PACKAGE DIMENSIONS 63-Ball TBGA (measured in millimeters) Top View 9.00 0.10 #A1 K9F2808U0C-VCB0,VIB0 K9F28XXX0C-DCB0,HCB0/DIB0,HIB0 DNU DNU ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 PIN CONFIGURATION (WSOP1) N.C N.C DNU N.C N.C N.C R DNU N.C Vcc Vss N.C DNU CLE ALE WE WP N.C N.C DNU N.C N.C PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F #1 #24 K9F2808U0C-VCB0,VIB0 K9F2808U0C-VCB0,FCB0/VIB0,FIB0 ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 (K9F2808X0C) I/O pins float to high-z when the chip is deselected or when the outputs are disabled. ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Figure 1-1. K9F2808X0C (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers A - A23 9 Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F2808X0C (X8) ARRAY ORGANIZATION 32K Pages 1st half Page Register ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Figure 1-2. K9F2816X0C (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers A - A23 9 Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9F2816X0C (X16) ARRAY ORGANIZATION 32K Pages ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 PRODUCT INTRODUCTION The K9F28XXX0C is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F28XXX0C-XCB0 Temperature Under Bias K9F28XXX0C-XIB0 K9F28XXX0C-XCB0 Storage Temperature K9F28XXX0C-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 VALID BLOCK Parameter Valid Block Number NOTE : K9F28XXX0C 1. The may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits or program factory-marked bad blocks ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 AC Timing Characteristics for Command / Address / Data Input Parameter Symbol CLE Set-up Time t CLE Hold Time t CE Setup Time CE Hold Time WE Pulse Width t ALE Setup Time t ALE Hold Time t Data Setup Time Data Hold Time Write Cycle Time ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Pointer Operation of K9F2808X0C(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Pointer Operation of K9F2816X0C(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’ 00h’ command sets the pointer to ’ A’ area(0~255word), and ’ 50h’ command sets the pointer to ’ B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte/264word page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addi- tion, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Device K9F2808X0C(X8 device) K9F2816X0C(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. 2. I/O8~15 are used only for data bus. * Command Latch Cycle CLE CE WE ALE I/Ox * Address Latch Cycle CLE ALE I/Ox K9F2808U0C-VCB0,VIB0 I/O I/ ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 * Input Data Latch Cycle CLE CE t ALS ALE I/Ox * Serial access Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load. K9F2808U0C-VCB0,VIB0 DIN 0 ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 * Status Read Cycle CLE I/Ox READ1 OPERATION (READ ONE PAGE) CLE ALE RE N Address Read I/Ox A0~A7 CMD Column Address R/B X8 device : m = 528 , Read CMD = 00h or 01h X16 device : m = 264 , Read CMD = 00h K9F2808U0C-VCB0,VIB0 t CLR t CLS ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE N Address Read I/Ox Col. Add CMD Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/Ox 50h Col. Add R/B M Address X8 device : A X16 device : A K9F2808U0C-VCB0,VIB0 On K9F2808U0C_Y,P or K9F2808U0C_V,F CE must be held ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00h Row Add1 I/Ox Col. Add R/B M PAGE PROGRAM OPERATION CLE ALE RE N Address I/Ox 80h Col. Add Row Add1 Sequential Data Column Input Command Address R/B K9F2808U0C-VCB0,VIB0 (only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block) ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h A9~A16 Page(Row) Address R/B Auto Block Erase Setup Command K9F2808U0C-VCB0,VIB0 (ERASE ONE BLOCK A17~A23 DOh Busy Erase Command 24 FLASH MEMORY t BERS 70h I/O 0 I/O =0 Successful Erase 0 Read Status ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command K9F2808U0C-VCB0,VIB0 REA 00h Address. 1cycle Device K9F2808Q0C K9F2808U0C K9F2816Q0C K9F2816U0C 25 FLASH MEMORY Device ECh Code* Maker Code Device Code Device Code* 33h 73h ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Figure 9. Read2 Operation CLE CE WE ALE R/B RE I/Ox Start Add.(3Cycle) 50h X8 device : X16 device : device : Don’ t care 4 7 X16 device : are "L" Figure 8-1. Sequential Row Read1 Operation (only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block ) ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Figure 9-1. Sequential Row Read2 Operation (GND Input=Fixed Low) (only for K9F2808U0C-Y,P and K9F2808U0C-V,F valid wihin a block) R/B I/Ox Start Add.(3Cycle) 50h & Don t Care) K9F2808U0C-VCB0,VIB0 Data Output 1st ~ A23 9 Data Field ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 264 (X8 device) or ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 12 shows the operation sequence. ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading ...

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... K9F2808Q0C-DCB0,DIB0 K9F2816Q0C-DCB0,DIB0 K9F2808U0C-YCB0,YIB0 K9F2816U0C-YCB0,YIB0 K9F2808U0C-DCB0,DIB0 K9F2816U0C-DCB0,DIB0 Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device) or 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V ...