73K224L-28IH TDK [TDK Electronics], 73K224L-28IH Datasheet

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73K224L-28IH

Manufacturer Part Number
73K224L-28IH
Description
V.22bis/V.22/V.21/ Bell 212A/Bell 103 Single-Chip Modem
Manufacturer
TDK [TDK Electronics]
Datasheet

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DESCRIPTION
The 73K224L is a highly integrated single-chip
modem IC which provides the functions needed to
construct a V.22bis compatible modem, capable of
2400 bit/s full-duplex operation over dial-up lines. The
73K224L offers excellent performance and a high
level of functional integration in a single 28-pin DIP
and 44-pin TQFP package. This device supports
V.22bis, V.22, V.21, Bell 212A and Bell 103 modes of
operation,
asynchronous
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular single-chip microprocessors (80C51
typical) for control of modem functions through its 8-
bit multiplexed address/data bus or via an optional
serial control bus. An ALE control line simplifies
address
normally occur through a separate serial port. The
73K224L is pin and software compatible with the
73K212L and 73K222L single-chip modem ICs,
allowing system upgrades with a single component
change.
The 73K224L operates from a single +5V supply for
low power consumption.
The 73K224L is ideal for use in either free-standing or
integral system modem products where full-duplex
BLOCK DIAGRAM
demultiplexing.
allowing
communication.
both
Data
synchronous
The
communications
73K224L
(continued)
and
V.22bis/V.22/V.21/ Bell 212A/Bell 103
is
FEATURES
One-chip multi-mode V.22bis/V.22/V.21 and Bell
212A/103 compatible modem data pump
FSK (300 bit/s), DPSK (600, 1200 bit/s), or QAM
(2400 bit/s) encoding
Pin and software compatible with other TDK
Semiconductor
modems
Interfaces directly with standard microcontrollers
(80C51 typical)
Parallel microcontroller bus for modem control and
status monitoring functions
Selectable
buffer/debuffer
functions
All synchronous and asynchronous operating
modes (internal, external, slave)
Adaptive equalization for optimum performance
over all lines
Programmable transmit attenuation (16 dB, 1 dB
steps), selectable receive boost (+18 dB)
Call progress, carrier, answer tone, unscrambled
mark, S1, and signal quality monitors
DTMF, answer and guard tone generators
Test modes available: ALB, DL, RDL, Mark, Space,
Alternating bit, S1 pattern
CMOS technology for low power consumption
(typically 100 mW @ 5V) with power-down mode
(15 mW @ 5V)
TTL and CMOS compatible inputs and outputs
asynch/synch
Single-Chip Modem
Corporation
and
scrambler/descrambler
K-Series
with
73K224L
April 2000
internal
1-chip

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73K224L-28IH Summary of contents

Page 1

... ICs, allowing system upgrades with a single component change. The 73K224L operates from a single +5V supply for low power consumption. The 73K224L is ideal for use in either free-standing or integral system modem products where full-duplex BLOCK DIAGRAM V.22bis/V.22/V.21/ Bell 212A/Bell 103 FEATURES • ...

Page 2

... DPSK MODULATOR/DEMODULATOR The 73K224L modulates a serial bit stream into di-bit pairs that are represented by four possible phase shifts as prescribed by the Bell 212A/V.22 standards. The base-band signal is then filtered to reduce intersymbol interference on the bandlimited 2-wire PSTN line ...

Page 3

... DTMF tone pairs. The tone pair sent is determined by selecting TRANSMIT DTMF (bit D4) and the 4 DTMF bits (D0-D3) of the TONE register. Transmission of DTMF tones from TXA is gated by the TRANSMIT ENABLE bit of CR0 (bit D1) as with all other analog signals. 3 73K224L Single-Chip Modem with the AD0, AD1, and memory locations ...

Page 4

... CLK pin will be set to the crystal frequency. An internal pull down resistor permits power on reset using a capacitor to VDD. Write. A low on this informs the 73K224L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are active (low). ...

Page 5

... These pins are for the internal crystal oscillator requiring a 11.0592 MHz parallel mode crystal. Two capacitors from these pins to ground are also required for XTL2 I/O proper crystal operation. Consult crystal manufacturer for proper values. XTL2 can also be driven from an external clock. V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem 5 73K224L ...

Page 6

... ALE. Register CR0 controls the method by which data is transferred over the phone line. CR1 controls the interface between the microprocessor and the 73K224L internal state detect register REGISTER BIT SUMMARY which provides an indication of monitored modem status conditions. TR, the tone control register, ...

Page 7

... BOOST TX BAUD RX UNSCR. TXD 0 CLOCK DATA SOURCE OUTPUTS OUTPUTS 0=TXD PIN TXBAUD UNSCR. 1=TXALT BIT CLOCK DATA 73K224L Single-Chip Modem TRANSMIT TRANSMIT ANSWER/ MODE ENABLE ORIGINATE 0 0=DISABLE 0=ANSWER TXA OUTPUT 1=ORIGINATE 1=ENABLE TXA OUTPUT TEST TEST RESET MODE ...

Page 8

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem CONTROL REGISTER CR0 MODUL. MODUL. MODUL. 000 OPTION TYPE 1 TYPE 0 BIT NO. NAME D0 Answer/ Originate D1 Transmit Enable D5, D4, Transmit D3, D2 Mode D6,D5 Modulation Type TRANSMIT TRANSMIT MODE 2 MODE 1 CONDITION DESCRIPTION 0 Selects answer mode (transmit in high band, receive in low band) ...

Page 9

... CR1, CR2, CR3 and Tone) are reset to zero except CR3 bit D2. The output of the clock pin will be set to the crystal frequency. 0 Selects 11.0592 MHz crystal echo output at CLK pin. 1 Selects 16 X the data rate, output at CLK pin in DPSK/QAM modes only. 9 73K224L Single-Chip Modem D2 D1 TRANSMIT TRANSMIT MODE 0 ENABLE D3 ...

Page 10

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem CONTROL REGISTER 1 (continued TRANSMIT TRANSMIT CR1 PATTERN PATTERN 001 1 0 BIT NO. NAME D4 Bypass Scrambler D5 Enable Detect Interrupt D7, D6 Transmit Pattern DETECT REGISTER D7 D6 RECEIVE S1 DR LEVEL PATTERN 010 INDICATOR DETECT BIT NO. NAME D0 Signal Quality ...

Page 11

... Select Bell mode answer tone. Interacts with DR bit D2 and TR bit D5 Select CCITT mode answer tone. Interacts with DR bit D2 and TR bit D5. 11 Single-Chip Modem ANSWER CALL TONE PROG. DETECT DTMF 2 DTMF 1/ EXTENDED OVER- SPEED 73K224L D0 SIGNAL QUALITY INDICATOR -25 dBm0); can D0 DTMF 0/ ANSWER/ GUARD ...

Page 12

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem TONE REGISTER (continued RXD TRANSMIT TR OUTPUT GUARD 011 CONTR. TONE BIT NO. NAME D0 DTMF 0/ Answer/ Guard Tone D1 DTMF 1/ Extended Overspeed D2 DTMF 2/4 WIRE FDX DTMF 3 TRANSMIT TRANSMIT ANSWER DTMF TONE CONDITION DESCRIPTION interacts with bits D6, D5, and D4 as shown ...

Page 13

... Disable DTMF. 1 Activate DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions. 13 73K224L Single-Chip Modem D2 D1 DTMF 2/4 DTMF 1/ DTMF 0/ WIRE FDX EXTENDED ANSWER OVER- SPEED GUARD DTMF CODE TONES ...

Page 14

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem TONE REGISTER (continued RXD TRANSMIT TR OUTPUT GUARD 011 CONTR. TONE BIT NO. NAME D5 Transmit Answer Tone D6 Transmit Guard Tone D7 RXD Output Control CONTROL REGISTER CR2 0 SPEC REG 100 ACCESS BIT NO. NAME D0 Equalizer Enable ...

Page 15

... Only write zero to this bit. 0 TXCLK and RXCLK are driven. 1 TXCLK and RXCLK are tri-stated. Spec. Reg. Bit D3=1 Alternate TX data source. See Special Register. 15 73K224L Single-Chip Modem D2 D1 RESET TRAIN EQUALIZER DSP INHIBIT ENABLE D2 ...

Page 16

... NOTE: This register is "mapped" and is accessed by setting CR2 bit ONE and addressing CR3. This register provides functions to the 73K224L user that are not necessary in normal communications. Bits D7-D4 are read only, while D3-D0 are read/write. To return to normal CR3 access, CR2 bit D6 must be returned to a ZERO ...

Page 17

... Indicates Device 73K212AL, 73K321L or 73K322L 73K221AL or 73K302L 73K222AL, 73K222BL 73K224L 73K324L 73K224BL 73K324BL Undefined Mask in software 1 Indicates industrial temperature version 17 73K224L Single-Chip Modem ...

Page 18

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage Note: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. ...

Page 19

... CLK = 11.0592 MHz ISET Resistor = 2 M Operating with crystal oscillator, < capacitive load on CLK pin VI = VDD Reset = VDD IO = IOH Min IOUT = -0 IOUT = 1.6 mA RXD = GND Maximum permitted load All digital inputs 19 73K224L Single-Chip Modem MIN NOM MAX UNIT 0.8 2.0 VDD 3.0 ...

Page 20

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem ELECTRICAL SPECIFICATIONS DYNAMIC CHARACTERISTICS AND TIMING ( +85 C, VDD = recommended range unless otherwise noted.) PARAMETER QAM/DPSK Modulator Carrier Suppression Output Amplitude FSK Modulator/Demodulator Output Freq. Error Transmit Level TXA Output Distortion Output Bias Distortion at ...

Page 21

... Init Mode DPSK Mode TXA pin TXA pin; FSK Single Tone out for THD = - 0.3 to 3.4 kHz range 4 kHz, Guard Tones off 10 kHz, Guard Tones off 12 kHz, Guard Tones off 21 73K224L Single-Chip Modem MIN NOM MAX UNIT -48 -43 dBm0 2 25 ...

Page 22

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem DYNAMIC CHARACTERISTICS AND TIMING PARAMETER Anti Alias Low Pass Filter Out of Band Signal Energy (Defines Hybrid Trans- Hybrid loss requirements) Transmit Attenuator Range of Transmit Level Step Accuracy Output Impedance Clock Noise Carrier Offset Capture Range ...

Page 23

... WR width Address setup before WR Low Address hold after Rising Edge of WR Write Data hold after Falling Edge of EXCLK WR High after Falling Edge of EXCLK Data setup before Falling Edge of EXCLK Minimum Period 23 73K224L Single-Chip Modem MIN NOM MAX UNIT ...

Page 24

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem TIMING DIAGRAMS BUS TIMING DIAGRAM (PARALLEL CONTROL MODE ) TLL ALE RD WR TAL AD0-AD7 ADDRESS CS READ TIMING DIAGRAM (SERIAL CONTROL MODE ) T1 T2 EXCLK TRCLK RD TAR TRA A0-A2 ADDRESS TRD D0 DATA WRITE TIMING DIAGRAM (SERIAL CONTROL MODE) ...

Page 25

... RXA C6 K-SERIES 0.1 µF LOW C2 RXA 300 pF POWER FAMILY 1000 pF R7 43.2K TXA 0.1 µF 20K TXA - LM 1458 + U1B +5V V– C12 1 µF 25 73K224L Single-Chip Modem C1 390 pF R5 37.4K R4 20K - LM 1458 + U1A MIDCOM 671-8005 475 0.47 µF D3, D4 0.033 µF 250V 4.7V ZENER ...

Page 26

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem DIRECT ACCESS ARRANGEMENT (DAA) The telephone line interfaces show two examples of how the “hybrid” may be implemented. The split supply design (Figure typical two op-amp hybrid. The receive op-amp serves two purposes. It supplies gain to amplify the receive signal to the proper level for the modem’ ...

Page 27

... S/N ratios are held constant at the indicated values while the receive level is lowered from a very high to very low signal levels. The width of the “bowl” of these curves, taken at the BER point, is the measure of dynamic range. 27 73K224L Single-Chip Modem 2400 as ...

Page 28

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem 28 ...

Page 29

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem 29 73K224L ...

Page 30

... V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem MECHANICAL SPECIFICATIONS 28-Pin DIP 28-Pin PLCC 30 ...

Page 31

... MECHANICAL SPECIFICATIONS (continued) 44-Lead TQFP V.22bis/V.22/V.21/Bell 212A/Bell 103 Single-Chip Modem 31 73K224L ...

Page 32

... PLCC PINOUTS 23 ARE THE SAME THE 28-PIN DIP 28-Pin PLCC 73K224L-28IH ORDER NO. 73K224L-IP 73K224L-IH 73K224L-IGT 32 CAUTION: Use handling procedures necessary for a static sensitive component. 44-Lead TQFP 73K224L-IGT PACKAGE MARK 73K224L-IP 73K224L-IH 73K224L-IGT 04/24/00 - rev. E ...

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