ATF55143 HP [Agilent(Hewlett-Packard)], ATF55143 Datasheet - Page 15

• Manufacturer Part Number: ATF55143
• Description: Agilent ATF-55143 Low Noise Enhancement Mode Pseudomorphic HEMT in a Surface Mount Plastic Package
• Manufacturer: HP [Agilent(Hewlett-Packard)]

The values of resistors R1 and R2
are calculated with the following
formulas
R1 =
R2 =
Example Circuit
V
V
I
V
Choose I
normal expected gate leakage
current. I
chosen to be 0.5 mA for this
example. Using equations (1), (2),
and (3) the resistors are calcu-
lated as follows
R1 = 940
R2 = 4460
R3 = 28.6
Active Biasing
Active biasing provides a means
of keeping the quiescent bias
point constant over temperature
and constant over lot to lot
variations in de vice dc perfor-
mance. The advantage of the
active biasing of an enhancement
mode PHEMT versus a depletion
mode PHEMT is that a negative
power source is not required. The
techniques of active biasing an
enhancement mode device are
very similar to those used to bias
a bipolar junction transistor.
ds
DD
ds
gs
= 10 mA
= 0.47V
= 2.7V
= 3V
V
(V
I
gs
BB
ds
BB
p
BB
– V
to be at least 10X the
V
(2)
was conservatively
gs
gs
) R1
p
(3)
INPUT
Figure 2. Typical ATF-55143 LNA with
ActiveBiasing.
An active bias scheme is shown
in Figure 2. R1 and R2 provide a
constant voltage source at the
base of a PNP transistor at Q2.
The constant voltage at the base
of Q2 is raised by 0.7 volts at the
emitter. The constant emitter
voltage plus the regulated V
supply are present across resis-
tor R3. Constant voltage across
R3 provides a constant current
supply for the drain current.
Resistors R1 and R2 are used to
set the desired Vds. The com-
bined series value of these
resistors also sets the amount of
extra current consumed by the
bias network. The equations that
describe the circuit’s operation
are as follows.
V
R3 =
V
V
V
Rearranging equation (4)
provides the following formula
R2 =
E
B
B
DD
= V
= V
=
Zo
= I
R7
V
ds
E
R
R1 + R2
BB
R5
R6
C1
DD
– V
1
L1
+ (I
R1
(V
– V
I
(R1 + R2)
R1
C3
ds
C2
BE
DD
V
ds
E
B
Q1
L2
•
– V
p
p
C7
V
Q2
R4)
15
DD
B
)
L3
R2
p
L4
C5
R4
C6
(5)
(1)
(3)
(4)
(2)
(4A)
C4
R3
Zo
DD
OUTPUT
Vdd
and rearranging equation (5)
provides the following formula
R1 =
Example Circuit
V
V
I
R4 = 10
V
Equation (1) calculates the
required voltage at the emitter of
the PNP transistor based on
desired V
resistor R4 to be 2.8V. Equation
(2) calculates the value of resis-
tor R3 which determines the
drain current I
R3 =20 . Equation (3) calculates
the voltage required at the
junction of resistors R1 and R2.
This voltage plus the step-up of
the base emitter junction deter-
mines the regulated V
tions (4) and (5) are solved
simultaneously to determine the
value of resistors R1 and R2. In
the example R1=4200
R2 =180 0 . R7 is chosen to be
1k . This resistor keeps a small
amount of current flowing
through Q2 to help maint ain bias
stability. R6 is chosen to be
10k . This value of resistance is
necessary to limit Q1 gate
current in the presence of high
RF drive levels (especially when
Q1 is driven to the P
compression point). C7 provides
a low frequency bypass to keep
noise from Q2 effecting the
operation of Q1. C7 is typically
0.1 F.
ds
DD
ds
BE
= 10 mA
= 2.7V
= 3V
= 0.7V
I
BB
ds
(
1 +
and I
V
DD
ds
I
V
BB
. In the example
DD
ds
= 0.5 mA
V
– V
through
B
1dB
ds
B
. Equa-
gain
and
)
p
9
(5A)