ZL50012/GDC ZARLINK [Zarlink Semiconductor Inc], ZL50012/GDC Datasheet - Page 38
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ZL50012/GDC
Manufacturer Part Number
ZL50012/GDC
Description
Flexible 512-ch Digital Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50012GDC.pdf
(65 pages)
External Read/Write Address: 100
15 - 9
Reset Value: 0000
Bit
SICR0
SICR1
SICR2
SICR3
SICR4
SICR5
SICR6
SICR7
8
7
6
5
15
0
0
0
0
0
0
0
0
STIN#QEN3
STIN#QEN2
STIN#QEN1
STIN#QEN0
H
Unused
Name
14
0
0
0
0
0
0
0
0
Table 20 - Stream Input Control Register 0 to 7 (SICR0 to SICR7)
13
0
0
0
0
0
0
0
0
H
,
102
12
0
0
0
0
0
0
0
0
H
Reserved. In normal functional mode, these bits MUST be set to zero.
Quadrant Frame 3 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch24 to
31, Ch48 to 63 and Ch96 to 127 for the 2.048 Mb/s, 4.096 Mb/s and
8.192 Mb/s mode respectively.
Quadrant Frame 2 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch16 to
23, Ch32 to 47 and Ch64 to 95 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
mode respectively.
Quadrant Frame 1 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch8 to 15,
Ch16 to 31 and Ch32 to 63 for the 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s
mode respectively.
Quadrant Frame 0 Enable. When this bit is low, the device is in normal
operation mode. When this bit is high, the LSB of every channel in this
quadrant frame is replaced by "1". This quadrant frame is defined as Ch0 to 7,
Ch0 to 15 and Ch0 to 31 for 2.048 Mb/s, the 4.096 Mb/s and 8.192 Mb/s mode
respectively.
,
104
11
0
0
0
0
0
0
0
0
H
,
106
10
0
0
0
0
0
0
0
0
H
Zarlink Semiconductor Inc.
,
108
ZL50012
9
0
0
0
0
0
0
0
0
H
,
41
10A
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
QEN3
QEN3
QEN3
QEN3
QEN3
QEN3
QEN3
QEN3
8
H
,
10C
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
QEN2
QEN2
QEN2
QEN2
QEN2
QEN2
QEN2
QEN2
7
H
,
Description
STIN0
QEN1
STIN1
QEN1
STIN2
QEN1
STIN3
QEN1
STIN4
QEN1
STIN5
QEN1
STIN6
QEN1
STIN7
QEN1
10E
6
H
,
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
QEN0
QEN0
QEN0
QEN0
QEN0
QEN0
QEN0
QEN0
5
STIN0
SMP1
STIN1
SMP1
STIN2
SMP1
STIN3
SMP1
STIN4
SMP1
STIN5
SMP1
STIN6
SMP1
STIN7
SMP1
4
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
SMP0
3
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
DR2
DR2
DR2
DR2
DR2
DR2
DR2
DR2
2
Data Sheet
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
DR1
DR1
DR1
DR1
DR1
DR1
DR1
DR1
1
STIN0
STIN1
STIN2
STIN3
STIN4
STIN5
STIN6
STIN7
DR0
DR0
DR0
DR0
DR0
DR0
DR0
DR0
0