ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 18

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

B6, C6, D5,
C5, C4, E3,
C2, B2, D2,
N4, P4, R4,
D4, B4, B3,
F3, F4, E2,
PBGA Pin
R15, M15,
D13, D15,
P11, R14,
L15, L13,
L14, E14,
P5, N13,
Number
C15
B11
F2
LQFP Pin
179, 180,
181, 182,
183, 184,
185, 187,
198, 200,
201, 202,
203, 204,
116, 117,
205, 206
Number
74, 115,
6, 7, 9,
10, 51,
52, 53,
54, 70,
72, 73,
154
118
STio 0 - 15
Pin Name
STi0 - 15
CKi
Zarlink Semiconductor Inc.
ST-BUS/GCI-Bus Clock Input (5 V-Tolerant Schmitt Triggered
Input)
This pin accepts a 4.096 MHz, 8.192 MHz or 16.384 MHz clock.
The clock frequency associated with twice the highest input or
output data rate must be applied to this pin when the device is
operating in either Divided Slave mode or Master mode. The
exception is if the device is operating in Master mode with
loopback (i.e., CKi_LP is set in the Control Register). In that case,
this input must be tied high or low externally. The clock frequency
associated with twice the highest input data rate must be applied
to this pin when the device is operating in Multiplied Slave mode.
In all modes of operation (except Master mode with loopback),
when data is running at 16.384 Mbps, a 16.384 MHz clock must be
used. By default, the clock falling edge defines the input frame
boundary, but the device allows the clock rising edge to define the
frame boundary by programming the CKINP bit in the Control
Register (CR).
Serial Input Streams 0 to 15 (5 V-Tolerant Inputs with Enabled
Internal Pull-downs)
The data rate of each input stream can be selected independently
using the Stream Input Control Registers (SICR[n]). In the
2.048 Mbps mode, these pins accept serial TDM data streams at
2.048 Mbps with 32 channels per frame. In the 4.096 Mbps mode,
these pins accept serial TDM data streams at 4.096 Mbps with 64
channels per frame. In the 8.192 Mbps mode, these pins accept
serial TDM data streams at 8.192 Mbps with 128 channels per
frame. In the 16.384 Mbps mode, these pins accept TDM data
streams at 16.384 Mbps with 256 channels per frame.
Serial Output Streams 0 to 15 (5 V-Tolerant Slew-Rate-Limited
Three-state I/Os with Enabled Internal Pull-downs)
The data rate of each output stream can be selected
independently using the Stream Output Control Registers
(SOCR[n]). In the 2.048 Mbps mode, these pins output serial TDM
data streams at 2.048 Mbps with 32 channels per frame. In the
4.096 Mbps mode, these pins output serial TDM data streams at
4.096 Mbps with 64 channels per frame. In the 8.192 Mbps mode,
these pins output serial TDM data streams at 8.192 Mbps with 128
channels per frame. In the 16.384 Mbps mode, these pins output
serial TDM data streams at 16.384 Mbps with 256 channels per
frame.These output streams can be used as bi-directionals by
programming BDL (bit 6) of Internal Mode Selection (IMS) register.
ZL50015
18
Description
Data Sheet