ZL50015GAC ZARLINK [Zarlink Semiconductor Inc], ZL50015GAC Datasheet - Page 42

• Manufacturer Part Number: ZL50015GAC
• Description: Enhanced 1 K Digital Switch with Stratum 4E DPLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

With a preferred reference, if more than two references are required, or the two references are not in consecutive
order, or the roles of the two references need to be interchanged, then external software is required to manually
control the reference switching of the DPLL (by monitoring the reference failure status and reprogramming the
device accordingly).
12.1.4
In freerun mode, the DPLL generates a fixed output frequency based on the crystal oscillator frequency. To meet
Stratum 4E, the accuracy of the circuitry for the freerunning output clock must be 32 ppm or better.
12.1.5
DPLL_IRM (bit 0) in the DPLL Control Register (DPLLCR) enables the internal reset mode. In the internal reset
mode, the DPLL module is disabled to save power. The circuit will be reset continuously and no output clocks will
be generated. When the internal DPLL module is in the internal reset mode, all registers remain accessible. Note
that applying the DPLL reset does not reset the DPLL registers: they preserve the values that they had prior to
entering reset.
13.0
13.1
The DPLL is capable of synchronizing to one of the following input frequencies:
13.2
The input frequencies of REF 0 - 3 can be automatically detected or programmed independently by the Reference
Frequency Register (RFR) if RFRE (bit 1) in the DPLL Control Register (DPLLCR) is set. The detected frequency of
the selected reference is indicated in the Reference Change Status Register (RCSR). In addition, the detected
frequencies of all four references are indicated in the Reference Frequency Status Register (RFSR). See Table 26
on page 63, Table 27 on page 64, Table 35 on page 71 and Table 41 on page 77 for the detailed bit description of
the DPLL Control Register (DPLLCR), Reference Frequency Register (RFR), Reference Change Status Register
(RCSR) and Reference Frequency Status Register (RFSR), respectively.
Input Frequencies
Input Frequencies Selection
DPLL Frequency Behaviour
Freerun Mode
DPLL Internal Reset Mode
Table 9 - DPLL Input Reference Frequencies
Zarlink Semiconductor Inc.
1.544 MHz (DS1)
2.048 MHz (E1)
ZL50015
16.384 MHz
4.096 MHz
8.192 MHz
19.44 MHz
8 kHz
42
Data Sheet