AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 19

• Manufacturer Part Number: AM79C90JCTR
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: AMD [Advanced Micro Devices]

PROGRAMMING
This section defines the Control and Status Registers
and the memory data structures required to program the
Am79C90 (C-LANCE).
Programming the Am79C90 (C-LANCE)
The Am79C90 (C-LANCE) is designed to operate in an
environment that includes close coupling with local
memory and microprocessor (HOST). The Am79C90
C-LANCE is programmed by a combination of registers
and data structures resident within the C-LANCE and
memory registers. There are four Control and Status
Registers (CSRs) within the C-LANCE which are pro-
grammed by the HOST device. Once enabled, the
C-LANCE has the ability to access memory locations to
acquire additional operating parameters.
The Am79C90 has the ability to do independent buffer
management as well as transfer data packets to and
from the Ethernet. There are three memory structures
accessed by the Chip:
In general, the programming sequence of the C-LANCE
may be summarized as:
Initialization Block—12 words in contiguous mem-
ory starting on a word boundary. It also contains
the operating parameters necessary for device op-
eration. The initialization block is comprised of:
— Mode of Operation
— Physical Address
— Logical Address Mask
— Location to Receive and Transmit Descriptor
— Number of Entries in Receive and Transmit
Receive and Transmit Descriptor Rings—Two ring
structures, one for incoming and outgoing packets.
Each entry in the rings is 4 words long and each
entry must start on a quadword boundary. The De-
scriptor Rings are comprised of:
— The address of a data buffer
— The length of that data buffer
— Status information associated with the buffer
Data Buffers—Contiguous portions of memory
reserved for packet buffering. Data buffers may
begin on arbitrary byte boundaries.
Program the C-LANCE’s CSRs by a host device to
locate an initialization block in memory. The byte
control, byte address, and address latch enable
modes are also defined here.
Rings
Descriptor Rings
P R E L I M I N A R Y
Am79C90
CONTROL AND STATUS REGISTERS
There are four Control and Status Registers (CSRs) on
the chip. The CSRs are accessed through two bus ad-
dressable ports, an address port (RAP) and a data port
(RDP).
Accessing the Control and Status
Registers
The CSRs are read (or written) in a two step operation.
The address of the CSR to be accessed is written into
the RAP during a bus slave transaction. During a subse-
quent bus slave transaction, the data being read from
(or written into) the RDP is read from (or written into) the
CSR selected in the RAP.
Once written, the address in RAP remains unchanged
until rewritten.
To distinguish the data port from the address port, a dis-
crete input pin is provided.
15
Bit
15:00
ADR Input Pin
Register Data Port (RDP)
The C-LANCE loads itself with the information con-
tained within the initialization block.
The C-LANCE accesses the descriptor rings for
packet handling.
H
L
CSR Data
Name
Port
Register Data Port (RDP)
Register Address Port (RAP)
CSR DATA
Description
Writing data into RDP writes the data
into the CSR selected in RAP. Read-
ing the data from the RDP reads the
data from the CSR selected in RAP.
CSR
sible only when the STOP bit of
CSR
If the STOP bit is not set while at-
tempting to access CSR
CSR
READY, but a READ operation will
return undefined data. WRITE op-
eration is ignored.
1
0
3
, CSR
, the C-LANCE will return
is set.
2
and CSR
3
17881B-13
1
AMD
are acces-
, CSR
2
19
or
0