AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 8
![no-image](/images/no-image-200.jpg)
AM79C90JCTR
Manufacturer Part Number
AM79C90JCTR
Description
CMOS Local Area Network Controller for Ethernet (C-LANCE)
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C90JCTR.pdf
(62 pages)
- Current page: 8 of 62
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DAL0–DAL15
FUNCTIONAL DESCRIPTION
The parallel interface of the CMOS Local Area Network
Controller for Ethernet (C-LANCE) has been designed
to be “friendly” or easy to interface to a variety of popular
microprocessors. These microprocessors include the
Am29000, 80x86, 680x0, Z8000 and LSI-11. The
C-LANCE has a 24-bit wide linear address space when
it is in the Bus Master Mode. A programmable mode of
operation allows byte addressing in one of two ways:
a Byte/Word control signal compatible with the 80x86
and Z8000 or an Upper Data Strobe and Lower Data
8
CPU
A16–A23
AMD
ALE
Buffer
Buffer
Figure 1. C-LANCE/CPU Interfacing Multiplexed Bus
DAL0–DAL15 A16–A23 Control
Bits 0–15
Data and
Address
Address
16–23
P R E L I M I N A R Y
Bits
Am79C90
Control
Strobe signal compatible with microprocessors such as
the 68000. A programmable polarity on the Address
Strobe signal eliminates the need for external logic. The
C-LANCE interfaces with both multiplexed and de-
multiplexed data busses and features control signals for
address/data bus transceivers. The C-LANCE is pin-for-
pin compatible with AMD’s LANCE device (Am7990).
Please refer to Appendix B for a complete comparison
between the C-LANCE and LANCE devices.
Buffer
A16–A23
ALE
A16–A23
DAL0 – DAL15
Latch
Decoder
C-LANCE
ALE
ADR
CS
17881B-5
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