AM79C90JCTR AMD [Advanced Micro Devices], AM79C90JCTR Datasheet - Page 26

• Manufacturer Part Number: AM79C90JCTR
• Description: CMOS Local Area Network Controller for Ethernet (C-LANCE)
• Manufacturer: AMD [Advanced Micro Devices]

The Broadcast address, which consists of all ones is a
special multicast address. Packets addressed to the
broadcast address must be received by all nodes. Since
broadcast packets are usually more common than other
multicast packets, the broadcast address should be the
first address in the multicast address list.
The Broadcast address does not go through the Logical
Address Filter and is always enabled. If the Logical Ad-
dress Filter is loaded with all zeroes, all incoming logical
addresses except broadcast will be rejected. The multi-
cast addressing in external loopback is operational only
when DTCR in the mode register is set to 1.
47
*Match - 1, the packet is accepted
Receive Descriptor Ring Pointer
26
Match - 0, the packet is rejected
Destination
Address
31
Figure 7. Logical Address Filter Operation
AMD
29 28 24 23
1 0
“1”
RES
RLEN
CRC
Gen
Enable
31
32-Bit Resultant CRC
6
26
000 ‘(Quadword
RDRA (23:03)
Select
MUX
64
Boundary)’
63
0
Logical Address
17881B-22
17881B-23
3
Filter
2 0
P R E L I M I N A R Y
Match*
Am79C90
0
Bit
31:29
28:24
23:03
02:00
Transmit Descriptor Ring Pointer
31:29
28:24
23:03
02:00
31
29 28 24 23
RDRA
Name
TDRA
RLEN
TLEN
RES
RES
RES
TLEN
Description
RECEIVE RING LENGTH is the
number of entries in the receive ring
expressed as a power of two.
RESERVED. Read as zeroes. Write
as zeroes.
RECEIVE DESCRIPTOR RING AD-
DRESS is the base address (lowest
address) of the Receive Descriptor
Ring.
MUST BE ZEROES. These bits are
RDRA (02:00) and must be zeroes
because the Receive Ring is aligned
on a quadword boundary.
TRANSMIT RING LENGTH is the
number of entries in the Transmit
Ring expressed as a power of two.
RESERVED. Read as zeroes. Write
as zeroes.
TRANSMIT DESCRIPTOR RING
ADDRESS is the base address (low-
est address) of the Transmit De-
scriptor Ring.
MUST BE ZEROES. These bits are
TDRA (02:00) and must be zeroes
because the Transmit Ring is
aligned on a quadword boundary.
RLEN
TLEN
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
000 ‘(Quadword
TDRA (23:03)
Number of Entries
Number of Entries
Boundary)’
17881B-24
128
128
16
32
64
16
32
64
3
1
2
4
8
1
2
4
8
2 0