AM79C940KCW AMD [Advanced Micro Devices], AM79C940KCW Datasheet - Page 103

• Manufacturer Part Number: AM79C940KCW
• Description: Media Access Controller for Ethernet (MACE)
• Manufacturer: AMD [Advanced Micro Devices]

AC WAVEFORMS
Notes:
1. TDTREQ will be asserted for two write cycles (4 SCLK cycles) minimum.
2. TDTREQ will deassert 1 SCLK cycle after EOF is detected (S2/S3 edge).
3. When EOF is written, TDTREQ will go inactive for 1 SCLK cycle minimum.
Note: TXDAT+ is the internal version of the signal, and is shown for clarification only.
STDCLK
(EDSEL = 0)
(EDSEL = 1)
TXDAT+
(Note 1)
XTAL1
TXEN
TDTREQ
DO+
DO–
DO±
SCLK
SCLK
EOF
S1
S1
S2
S2
9
S3
S3
1
Host System Interface—TDTREQ Write Timing
S0
S0
53
AUI Transmit Timing—Start of Packet
S1
S1
46
S2
S2
1
0
S3
S3
Am79C940
Note 1
1
54
S0
S0
42
S1
S1
43
1
S2
S2
S3
S3
Note 2
47
55
S0
S0
S1
S1
0
S2
S2
Note 3
S3
S3
16235C-31
16235C-30
AMD
S0
S0
1
103