AM79C940KCW AMD [Advanced Micro Devices], AM79C940KCW Datasheet - Page 120

• Manufacturer Part Number: AM79C940KCW
• Description: Media Access Controller for Ethernet (MACE)
• Manufacturer: AMD [Advanced Micro Devices]

attribute INSTRUCTION_PRIVATE of am79c940 : entity is “Selftst”;
attribute IDCODE_REGISTER of am79c940 : entity is
attribute REGISTER_ACCESS of am79c940 : entity is
attribute BOUNDARY_CELL of am79c940 : entity is “BC_1,BC_4”;
attribute BOUNDARY_LENGTH of am79c940 : entity is 99
– num cell
“0000” &
“1001010000000000” &
”00000000001” & – 11 bit manufacturer
“1”;
“Boundary (Extest, Sample, Selftst),” &
“Bypass (Bypass, Tribyp, Setbyp),” &
“Idcode (Idcode)”;
“98 (BC_1,
“97 (BC_1,
“96 (BC_1,
“95 (BC_1,
“94 (BC_1,
“93 (BC_1,
“92 (BC_1,
“91 (BC_1,
“90 (BC_1,
“89 (BC_1,
“88 (BC_1,
“87 (BC_1,
“86 (BC_1,
“85 (BC_1,
“84 (BC_1,
“83 (BC_1,
“82 (BC_1,
“81 (BC_1,
“80 (BC_1,
“79 (BC_1,
“78 (BC_1,
“77 (BC_1,
“76 (BC_1,
“75 (BC_1,
“74 (BC_1,
“73 (BC_1,
“72 (BC_1,
“71 (BC_1,
“70 (BC_1,
“69 (BC_1,
“68 (BC_1,
“67 (BC_1,
“66 (BC_1,
“65 (BC_1,
“64 (BC_1,
“63 (BC_1,
“62 (BC_1,
port
– 4 bit version
*,
*,
*,
*,
*,
*,
*,
*,
*,
DXRCV_L,
*,
EDSEL,
TXDAT1,
TXDAT1,
TXDAT0,
*,
STDCLK,
STDCLK,
*,
TXEN_L,
TXEN_L,
*,
CLSN,
CLSN,
*,
RXDAT,
RXDAT,
*,
RXCRS,
RXCRS,
*,
SRDCLK,
SRDCLK,
*,
EAM_R,
SRD,
SF_BD,
– 16 bit part number
– mandatory LSB
function
internal,
internal,
internal,
internal,
internal,
internal,
internal,
internal,
internal,
output3,
control,
control,
control,
control,
input,
output3,
control,
control,
control,
control,
output3,
safe
input,
input,
output3,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
input,
output3,
Am79C940
(ccell
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
0),” &
X,
0),” &
0),” &
0),” &
0),” &
X,
0),” &
0),” &
0),” &
0),” &
X,
88,
X,
X,
X,
X,
0),” &
74,
X,
X,
X,
61,
X,
disval
– COL_SQL
– AUI_NSQ
– XMTD
– AUIEN
– TXD0L
– TXP0L
– TXEN
– PSQ_O xor FIXPOL
– CLK20
0,
– TRI PWDNBAR
1),” &
1),” &
83,
83,
– TRI TXDAT+/TXDAT–
0),” &
80,
– TRI STDCLK
0),” &
77,
– TRI TXEN_L
0,
– TRI CLSN
0),” &
71,
– TRI RXDAT
0),” &
68,
– TRI RXCRS
0),” &
65,
– TRI SRDCLK
0),” &
0,
61,
Z),” &
0,
0,
0,
0,
Z),” &
0,
0,
0,
Z),” &
0,
rslt)
Z),” &
Z),” &
Z),” &
Z),” &
Z),” &
Z),” &
Z),” &
Z),” &
AMD
B-3