ZL50062 ZARLINK [Zarlink Semiconductor Inc], ZL50062 Datasheet - Page 49
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ZL50062
Manufacturer Part Number
ZL50062
Description
16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50062.pdf
(68 pages)
- Current page: 49 of 68
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13.8
Address 1001
This register allows the bit rate of all the input and output streams to be set to 2.048, 4.096, 8.192 or 16.384 Mbps.
The BRR register is configured as follows:
13.9
Address 3FFF
The Device Identification Register stores the binary value of the silicon revision number and the Device ID. This
register is read-only. The DIR register is configured as follows:
15:3
2:1
Bit
15:8
Bit
7:4
2:0
0
3
Bit Rate Register
Device Identification Register
Reserved
Reserved
BRS[1:0]
Name
Reserved
Reserved
H
DID[2:0]
H
RC[3:0]
Name
.
Reset
Value
0
0
0
Output Control with ODE pin and OSB bit
Table 25 - Device Identification Register (DIR) Bits
Reserved
Must be set to 0 for normal operation
Bit Rate Selector
These 2 bits define the bit rate of all the input and output ST-BUS streams, which
can operate in either 2.048, 4.096, 8.192 or 16.384 Mbps.
Reserved
Must be set to 0 for normal operation
Reset Value
Table 24 - Bit Rate Register (BRR) Bits
0000
110
0
0
Bit 2
0
0
1
1
Zarlink Semiconductor Inc.
ZL50062/4
Bit 1
Reserved
Will read 0 in normal operation
Revision Control Bits
Reserved
Will read 0 in normal operation
Device ID
0
1
0
1
49
Description
Bit Rate of all ST-BUS Streams
16.384Mbps
2.048Mbps
4.096Mbps
8.192Mbps
Description
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