AM79C973VCW AMD [Advanced Micro Devices], AM79C973VCW Datasheet - Page 170
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AM79C973VCW
Manufacturer Part Number
AM79C973VCW
Description
Manufacturer
AMD [Advanced Micro Devices]
Datasheet
1.AM79C973VCW.pdf
(304 pages)
- Current page: 170 of 304
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170
LEDPOL
LEDDIS
LED Polarity. When this bit has
the value 0, then the LED pin will
be driven to a LOW level whenev-
er the OR of the enabled signals
is true, and the LED pin will be
disabled and allowed to float high
whenever the OR of the enabled
signals is false (i.e., the LED out-
put will be an Open Drain output
and the output value will be the
inverse of the LEDOUT status
bit.).
LED Disable. This bit is used to
disable the LED output. When
LEDDIS has the value 1, then the
LED output will always be dis-
abled. When LEDDIS has the val-
ue 0, then the LED output value
will be governed by the LEDOUT
and LEDPOL values.
The logical value of the LEDOUT
status signal is determined by the
settings of the individual Status
Enable bits of the LED register
(bits 8 and 6-0).
Read accessible always. This bit
is read only; writes have no ef-
fect. LEDOUT is unaffected by
H_RESET, S_RESET, or STOP.
When this bit has the value 1,
then the LED pin will be driven to
a HIGH level whenever the OR of
the enabled signals is true, and
the LED pin will be driven to a
LOW level whenever the OR of
the enabled signals is false (i.e.,
the LED output will be a Totem
Pole output and the output value
will be the same polarity as the
LEDOUT status bit).
The setting of this bit will not ef-
fect the polarity of the LEDOUT
bit for this register.
Read/Write accessible always.
LEDPOL is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Read/Write accessible always.
LEDDIS is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
P R E L I M I N A R Y
Am79C973/Am79C975
12
11-10 RES
9
8
7
100E
MPSE
FDLSE
PSE
Full-Duplex Link Status Enable.
100 Mbps Enable. When this bit
is set to 1, a value of 1 is passed
to the LEDOUT bit in this register
when the Am79C973/Am79C975
controller is operating at 100
Mbps mode.
Read/Write accessible always.
100E is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Reserved locations. Written and
read as zeros.
Magic Packet Status Enable.
When this bit is set to 1, a value of
1 is passed to the LEDOUT bit in
this register when magic frame
mode is enabled and a magic
frame is detected on the network.
Read/Write accessible always.
MPSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Indicates the Full-Duplex Link
Test Status. When this bit is set,
a value of 1 is passed to the LED-
OUT signal when the Am79C973/
Am79C975 controller is function-
ing in a Link Pass state and full-
duplex operation is enabled.
When
Am79C975 controller is not func-
tioning in a Link Pass state with
full-duplex operation being en-
abled, a value of 0 is passed to
the LEDOUT signal.
Read/Write accessible always.
FDLSE is cleared by H_RESET
and is not affected by S_RESET
or setting the STOP bit.
Pulse Stretcher Enable. When
this bit is set, the LED illumination
time is extended for each new oc-
currence of the enabled function
for this LED output. A value of 0
disables the pulse stretcher.
Read/Write accessible always.
PSE is set to 1 by H_RESET and
is not affected by S_RESET or
setting the STOP bit.
the
Am79C973/
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