ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet - Page 42

• Manufacturer Part Number: ZL50073GAG2
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Each byte location of the BER Enable Memory contains one read/write BER counter enable (BCE) bit, mapped into
the D0 location. If the BCE bit is set, then the BER counter for the corresponding stream and timeslot is enabled for
the duration of that timeslot. If the BCE bit is cleared the counter is disabled.
14.3.2
There are a total of 128 Bit Error Counters, corresponding to the 128 serial input streams. Each count value is 32
bits wide, but only the least significant 16 bits are used. The most significant 16 bits of the bit error counters will
always read back zero. A write operation to any byte of the counter, including the 16 most significant bits, will clear
that counter.
Each bit error counter contains the number of single bit errors detected on the corresponding stream, since the
counter was last cleared. If the number of bit errors detected exceeds 65535 (decimal), the counter will hold that
value until it is cleared.
Input Group Data Rate
Table 22 - BER Enable Control Memory Stream Address Offset at Various Output Rates
BER Counters
65 Mbps
32 Mbps
16 Mbps
8 Mbps
Time-slot Range
0 - 1023
0 - 511
0 - 255
0 - 127
N/A
Zarlink Semiconductor Inc.
ZL50073
42
Input Streams
STiBn, Cn, Dn
STiCn, Dn
BERR
STiAn
STiAn
STiBn
STiAn
STiBn
STiCn
STiAn
STiBn
STiCn
STiDn
STiDn
Address Offset Range (Hex)
00000 - 003FF
00000 - 001FF
00200 - 003FF
00000 - 000FF
00100 - 001FF
00200 - 002FF
00300 - 003FF
00080 - 000FF
00180 - 001FF
00200 - 003FF
00000 - 0007F
00100 - 0017F
N/A
N/A
Data Sheet