ZL50073GAG2 ZARLINK [Zarlink Semiconductor Inc], ZL50073GAG2 Datasheet - Page 7

• Manufacturer Part Number: ZL50073GAG2
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps), and 128 Inputs and 128 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Change Summary
The following table captures the changes from the April 2005 issue.
The following table captures the changes from the July 2004 issue.
Page
Page
28
29
29
30
43
12
13
54
56
57
58
59
60
61
62
63
63
10.4.1, “Read Cycle“
Figure 10 "Read Cycle Operation"
10.4.2, “Write Cycle“
Figure 11 "Write Cycle Operation"
Table 23 “BER Counter Group and
Stream Address Mapping“
"Pin Description" - CKo0-3
"Pin Description" - DTA, WAIT
“AC Electrical Characteristics1 - FPi0-2
and CKi0-2 Timing“
Figure 13 "Frame Skew Timing Diagram" Added FPi1,2 frame pulse to Figure “Frame Skew Timing
(1) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (65.536 MHz)
Timing“
(2) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (32.768 MHz)
Timing“
(3) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (16.384 MHz)
Timing“
(4) “AC Electrical Characteristics1 -
FPO0-3 and CKO0-3 (8.192 MHz)
Timing“
“AC Electrical Characteristics - Output
Clock Jitter Generation“
“AC Electrical Characteristics1 - Serial
Data Timing2 to CKi“
Figure 16 "Serial Data Timing to CKi"
“AC Electrical Characteristics - Serial
Data Timing1 to CKo2“
Figure 17 "Serial Data Timing to CKo"
“AC Electrical Characteristics - CKo to
Other CKo Skew1“
Figure 18 "CKo to other CKo Skew"
Item
Item
Zarlink Semiconductor Inc.
ZL50073
Clarified WAIT signal description in Read Cycle.
Corrected WAIT signal tristate timing in Read Cycle.
Clarified WAIT signal description in Write Cycle.
Corrected WAIT signal tristate timing in write Cycle.
Corrected BER Counter Group and Stream Mapping
Addresses.
Added special requirement for using output clock at
65.536 MHz.
Added more detailed description to the DTA and WAIT
pins.
Added t
maximum values.
Diagram” to clarify frame boundary skew.
Added CKO0-3 and FPO0-3 setup and hold parameters for
all different clock rates.
Added this table to specify CKO0-3 jitter generation.
(1) Values of parameters t
t
(2) Separated parameter t
Added more detail to figure.
Values of parameters t
t
Added more detail to figure.
Added CKO skew parameters, t
Added figure to show t
SIPV,
SONV,
7
t
SIPZ
t
SOPZ
FPIS
and t
, t
and t
FPIH
SINZ
SONZ
(input frame pulse setup and hold)
are revised.
SOPS,
CKOS.
are revised.
Change
Change
SIPS,
CKD
t
SOPH,
into t
t
SIPH,
CKOS
CKDP
t
SONS,
t
.
SINS,
and t
t
SONH,
t
SINH,
CKDN.
Data Sheet
t
t
SINV,
SOPV,