ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 21

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

3.0
The following key applies to all tables:
3.1
All TDM Interface signals are 5 V tolerant.
All TDM Interface outputs are high impedance while System Reset is LOW.
All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be
safely left unconnected if not used.
3.1.1
TDM_STi[31:0]
TDM Interface
External Interface Description
Signal
ZL50111 Variant TDM Stream Connection
I
O
D
U
T
Input
Output
Internal 100 kΩ pull-down resistor present
Internal 100 kΩ pull-up resistor present
Tri-state Output
I/O
I D
Table 2 - TDM Interface ZL50111 Stream Pin Definition
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
D26
E25
D25
C26
C25
E20
F18
B25
E18
C22
A23
A21
C18
A19
B17
C16
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
21
B16
D14
B14
D13
C12
B11
C11
D11
A8
A6
D8
B5
C5
B3
E9
D5
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[31:0]
H.110:
H-MVIP: TDM_HDS[31:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [7:0] are used, with 128 channels
per stream. Streams [7:0] are used for J2,
and streams [1:0] are used for T3, E3 pr
STS-1.
TDM_D[31:0]
Description
Data Sheet