ZL50110 ZARLINK [Zarlink Semiconductor Inc], ZL50110 Datasheet - Page 30

• Manufacturer Part Number: ZL50110
• Description: 128, 256 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

M0_RBC0
M0_RBC1
M0_COL
M0_RXD[7:0]
M0_RXDV /
M0_RXD[8]
M0_RXER /
M0_RXD[9]
Signal
Table 9 - MII Port 0 Interface Package Ball Definition (continued)
I/O
I U
I U
I D
I U
I D
I D
Y24
AA25
Y25
[7]
[6]
[5]
[4]
V25
V26
W25
W24
U23
V24
Package Balls
Zarlink Semiconductor Inc.
ZL50110/11/14
[3]
[2]
[1]
[0]
MII Port 0
30
W26
U22
Y26
AA26
TBI - M0_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180°C out of phase with
M0_RBC1.
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
TBI - M0_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180°C out of phase with
M0_RBC0.
each rising edge of M0_RBC1 and
M0_RBC0, resulting in 125 MHz sample
rate.
GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
GMII/MII - M0_RXDV
Receive Data Valid. Active high. This
signal is clocked on the rising edge of
M0_RXCLK. It is asserted when valid data
is on the M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used
in conjunction with M0_RXD when
M0_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
Receive data is clocked at
Receive data is clocked at
Description
Data Sheet