ZL50110_08 ZARLINK [Zarlink Semiconductor Inc], ZL50110_08 Datasheet - Page 12

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ZL50110_08

Manufacturer Part Number
ZL50110_08
Description
128, 256, 512 and 1024 Channel CESoP Processors
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
The following table captures the changes from the April 2005 issue.
The following table captures the changes from the January 2005 issue.
The following table captures the changes from the October 2004 issue.
The following table captures the changes from the September 2004 issue.
12, 16, 19
47, 48
Page
Page
Page
Page
66
98
98
48
73
98
Section 3.6 and Section 3.7.2
Section 6.3
Figure 45
Figure 46
Section 3.7.1
Fig. 2 and Ball Signal
Assignment Table
DC Electrical Characteristics
Table and Output Levels Table
Section 13.3
Item
Item
Item
Item
ZL50110/11/12/14
Zarlink Semiconductor Inc.
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform
Clarified ZL50111 supports 3 MII ports, ZL50110/4 support 2 MII
ports.
Added external pull-up/pull-down resistor recommendations for
SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
Added Section 6.3 SYSTEM_CLK Considerations.
Clarified data sheet to indicate ZL50110/11/12/14 supports
clock recovery in both synchronous and asynchronous modes
of operation.
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
Added 5 kohm pulldown recommendation to GPIO signals.
Corrected Mx_LINKUP_LED pin assignment.
Changed Electrical Characteristics to differentiate between
3.3 V and 5 V tolerant signals.
New section added; Mx_LINKUP_LED Outputs.
12
Change
Change
Change
Change
Data Sheet

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