ZL50110_08 ZARLINK [Zarlink Semiconductor Inc], ZL50110_08 Datasheet - Page 90
![no-image](/images/no-image-200.jpg)
ZL50110_08
Manufacturer Part Number
ZL50110_08
Description
128, 256, 512 and 1024 Channel CESoP Processors
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50110_08.pdf
(112 pages)
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11.6.2
RXCLK period
RXCLK high wide time
RXCLK low wide time
RXCLK rise time
RXCLK fall time
RXD[3:0] setup time (RXCLK
rising edge)
RXD[3:0] hold time (RXCLK
rising edge)
RXDV input setup time
(RXCLK rising edge)
RXDV input hold time (RXCLK
rising edge)
RXER input setup time (RXCL
edge)
RXER input hold time (RXCLK
rising edge)
RXD[3:0]
RXCLK
MII Receive Timing
RXDV
RXER
Parameter
Table 36 - MII Receive Timing - 100 Mbps
Symbol
t
t
t
t
t
t
t
t
t
t
DVS
DVH
ERS
ERH
Figure 35 - MII Receive Timing Diagram
t
CC
CH
CR
DS
DH
CL
CF
ZL50110/11/12/14
Zarlink Semiconductor Inc.
t
t
DVS
DS
Min.
14
14
10
10
10
5
5
5
-
-
-
t
DH
90
t
CC
100 Mbps
t
Typ.
ERS
40
20
20
-
-
-
-
-
-
-
-
t
ERH
Max.
26
26
5
5
-
-
-
-
-
-
-
t
CLO
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CHI
t
DVH
Data Sheet
Notes
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