ZL50110_08 ZARLINK [Zarlink Semiconductor Inc], ZL50110_08 Datasheet - Page 34

• Manufacturer Part Number: ZL50110_08
• Description: 128, 256, 512 and 1024 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

M0_LINKUP_LED
M0_ACTIVE_LED
M0_GIGABIT_LED
M0_REFCLK
M0_RXCLK
M0_RBC0
M0_RBC1
Signal
I/O
I D
I U
I U
I U
O
O
O
Table 10 - MII Port 0 Interface Package Ball Definition
G24 on ZL50110/4
AB23 on ZL50111/2
AC26
H22
AA24
AB22
Y24
AA25
Package Balls
ZL50110/11/12/14
Zarlink Semiconductor Inc.
MII Port 0
34
LED drive for MAC 0 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 0 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
LED drive for MAC 0 to indicate operation at
Gbps
Logic 0 output = LED on
Logic 1 output = LED off
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M0_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M0_RXCLK.
GMII/MII - M0_RXCLK.
Accepts the following frequencies:
125.0 MHz
TBI - M0_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180°C out of phase with
M0_RBC1.
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
TBI - M0_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180°C out of phase with
M0_RBC0.
each rising edge of M0_RBC1 and
M0_RBC0, resulting in 125 MHz sample
rate.
25.0 MHz
Receive data is clocked at
Receive data is clocked at
MII
GMII 1 Gbps
Description
100 Mbps
Data Sheet