S71GL064A08 SPANSION [SPANSION], S71GL064A08 Datasheet - Page 132

• Manufacturer Part Number: S71GL064A08
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

Notes:
1. A write occurs during the overlap (t
2. t
3. t
4. t
130
Figure 62. Timing Waveform of Write Cycle(2) (CS# controlled, if BYTE# is Low, Ignore UB#/LB# Timing)
goes low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double
byte operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t
measured from the beginning of write to the end of write.
going high.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the CS1# going low to the end of write.
is measured from the end of write to the address change. t
UB#, LB#
UB#, LB#
Data out
Data out
Address
Address
Data in
Data in
CS1#
CS1#
WE#
WE#
CS2
CS2
Figure 63. Timing Waveform of Write Cycle(3) (UB#, LB# controlled)
WP
High-Z
High-Z
) of low CS1# and low WE#. A write begins when CS1# goes low and WE#
t
t
AS(3 )
AS(3)
A d v a n c e
S71GL064A based MCPs
t
t
AW
CW(2)
t
t
t
t
AW
WC
CW(2)
CW(2)
t
WC
t
t
I n f o r m a t i o n
BW
BW
t
WP(1)
t
WR
WP(1 )
applied in case a write ends as CS1# or WE#
t
DW
t
DW
Data Valid
Data Valid
t
WR(4 )
t
WR(4)
t
DH
t
DH
High-Z
High-Z
S71GL064A_00_A2 February 8, 2005
WP
is