S71GL064A08 SPANSION [SPANSION], S71GL064A08 Datasheet - Page 23

• Manufacturer Part Number: S71GL064A08
• Description: STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
• Manufacturer: SPANSION [SPANSION]

February 8, 2005 S71GL064A_00_A2
Standby Mode
Automatic Sleep Mode
RESET#: Hardware Reset Pin
Output Disable Mode
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect
mode. The system can then read autoselect codes from the internal register (which is sepa-
rate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode.
Refer to the
tion on page 41
When the system is not reading or writing to the device, it can place the device in the standby
mode. In this mode, current consumption is greatly reduced, and the outputs are placed in
the high impedance state, independent of the OE# input.
The device enters the CMOS standby mode when the CE# and RESET# pins are both held at
V
are held at V
standby current will be greater. The device requires standard access time (t
when the device is in either of these standby modes, before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current
until the operation is completed.
Refer to the
The automatic sleep mode minimizes Flash device energy consumption. The device automat-
ically enables this mode when addresses remain stable for t
mode is independent of the CE#, WE#, and OE# control signals. Standard address access
timings provide new data when addresses are changed. While in sleep mode, output data is
latched and always available to the system. Refer to the
60
The RESET# pin provides a hardware method of resetting the device to reading array data.
When the RESET# pin is driven low for at least a period of t
nates any operation in progress, tristates all output pins, and ignores all read/write
commands for the duration of the RESET# pulse. The device also resets the internal state
machine to reading array data. The operation that was interrupted should be reinitiated once
the device is ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET# pulse. When RESET# is held at V
the device draws CMOS standby current (I
V
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also
reset the Flash memory, enabling the system to read the boot-up firmware from the Flash
memory.
Refer to the AC Characteristics tables for RESET# parameters and to
diagram.
When the OE# input is at V
in the high impedance state.
IO
SS
for the automatic sleep mode current specification.
±0.3 V, the standby current will be greater.
± 0.3 V. (Note that this is a more restricted voltage range than V
A d v a n c e
“Autoselect Mode” section on page 29
“DC Characteristics” section on page 60
IH
, but not within V
sections for more information.
IH
I n f o r m a t i o n
, output from the device is disabled. The output pins are placed
S71GL064A based MCPs
IO
± 0.3 V, the device will be in the standby mode, but the
CC5
). If RESET# is held at V
and
for the standby current specification.
“Autoselect Command Sequence” sec-
“DC Characteristics” section on page
ACC
RP
, the device immediately termi-
+ 30 ns. The automatic sleep
IH
Figure 15
.) If CE# and RESET#
CE
IL
) for read access
but not within
for the timing
SS
±0.3 V,
21