S71PL512ND0JAW5B0 SPANSION [SPANSION], S71PL512ND0JAW5B0 Datasheet - Page 81

• Manufacturer Part Number: S71PL512ND0JAW5B0
• Description: Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

17 Pin Description
18 Power Up Sequence
19 Timing Diagrams
19.1
February 3, 2005 pSRAM_15_A2
Power Up
1. Apply power.
2. Maintain stable power (V
Note: After V
Note: After V
CS2
CS1#=high or CS2=low.
V
CS1#
CS2
V
CC
CC
1#
V
V
CC(Mi n )
CC(Mi n )
CC
CC
reaches V
reaches V
A0 – A22 (128M)
A0 – A19 (16M)
A0 – A20 (32M)
A0 – A21 (64M)
I/O0-I/O15
CS1#, CS2
Pin Name
LB#, UB#
V
V
CC
SS
P r e l i m i n a r y
WE#
OE#
DNU
CC
CC
NC
/V
/V
(Min.), wait 200 µs with CS1# high. Then the device gets into the normal operation.
(Min.), wait 200 µs with CS2 low. Then the device gets into the normal operation.
CCQ
SSQ
Figure 19.2. Power Up 2 (CS2 Controlled)
Power Up Mode
Figure 19.1 Power Up 1 (CS1# Controlled)
Power Up Mode
Min. 200μs
Min. 200 μs
CC
pSRAM Type 2
min.=2.7V) for a minimum 200 µs with
Normal Operation
Normal Operation
Not Connection
Address Inputs
Output Enable
Power Supply
Description
Lower/Upper
Data Inputs/
Write Enable
Byte Enable
Chip Select
Do Not Use
Outputs
Ground
I/O
I/O
—
—
—
—
I
I
I
I
I
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