S71PL512ND0JAW5B0 SPANSION [SPANSION], S71PL512ND0JAW5B0 Datasheet - Page 83

• Manufacturer Part Number: S71PL512ND0JAW5B0
• Description: Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

24 DC and Operating Characteristics
24.1
24.2 16M pSRAM
24.3 32M pSRAM
24.4 64M pSRAM
February 3, 2005 pSRAM_15_A2
Common
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms
from the time when standby mode is set up.
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms
from the time when standby mode is set up.
Note: Standby mode is supposed to be set up after at least one active operation after power up. ISB1 is measure after 60ms
from the time when standby mode is set up.
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Average Operating
Current
Standby Current
(CMOS)
Average Operating
Current
Standby Current
(CMOS)
Average Operating
Current
Standby Current
(CMOS)
Item
Item
Item
Item
I
I
I
(See Note)
(See Note)
CC2
CC2
(See Note)
CC2
Symbol
Symbol
Symbol
P r e l i m i n a r y
I
I
I
I
I
I
CC1
CC1
SB1
SB1
CC1
SB1
Async
Async
Page
Page
Async
Page
Symbol
V
V
I
I
LO
OH
LI
OL
Cycle time=1µs, 100% duty, I
LB#≤0.2V and/or UB#≤0.2V,
CS2≥V
Cycle time=Min, I
CS1#=V
UB#=V
Cycle time=t
CS1#=V
UB#=V
Other inputs=0-VCC
1. CS1# ≥ V
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Cycle time=1µs, 100% duty, I
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥V
Cycle time=Min, I
CS1#=V
UB#=V
Cycle time=t
CS1#=V
UB#=V
Other inputs=0-VCC
1. CS1# ≥ V
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
Cycle time=1µs, 100% duty, I
CS1#≤0.2V, LB#≤0.2V and/or UB#≤0.2V,
CS2≥V
Cycle time=Min, I
CS1#=V
UB#=V
Cycle time=t
CS1#=V
UB#=V
Other inputs=0-V
1. CS1# ≥ V
2. 0V ≤ CS2 ≤ 0.2V (CS2 controlled)
CC
CC
CC
IL
IL
IL
IL
pSRAM Type 2
IL
IL
-0.2V, V
IL
IL
-0.2V, V
IL
IL
, V
, V
, V
, V
-0.2V, V
IL
IL
, V
, V
, CS2=V
, CS2=V
, CS2=V
, CS2=V
WE#=V
, CS2=V
, CS2=V
IN
IN
IN
IN
CC
CC
IN
IN
CC
RC
RC
RC
=V
-V
=V
-V
CS1#=V
=V
-V
- 0.2, CS2 ≥ V
- 0.2, CS2 ≥ V
+3t
+3t
- 0.2, CS2 ≥ V
+3t
IH
IH
IH
IN
IH
IN
IH
IN
IH
IO
IO
IL
CC
or V
or V
IO
≤0.2V or V
IH
IH
≤0.2V or V
IH
IH
PC
PC
≤0.2V or V
or V
or V
or V
IH
IH
PC
=0mA, 100% duty,
=0mA, 100% duty,
or V
=0mA, 100% duty,
or LB#=UB#=V
, I
, I
LB#=V
LB#=V
LB#=V
LB#=V
, I
LB#=V
LB#=V
Test Conditions
Test Conditions
IH
Test Conditions
IL
IL
IO
IO
IL
IL
IL
IO
IL
Test Conditions
=0 mA, 100% duty,
=0mA, 100% duty,
V
or CS2=V
=0mA, 100% duty,
IN
I
I
OH
OL
IL
IL
IL
IL
=V
CC
CC
IL
IL
IN
IN
CC
IN
=-1.0mA
=2.1mA
IO
IO
and/or
and/or
and/or
and/or
IO
≥VCC-0.2V
≥VCC-0.2V
SS
and/or
and/or
- 0.2V (CS1# controlled) or
- 0.2V (CS1# controlled) or
≥VCC-0.2V
- 0.2V (CS1# controlled) or
=0mA, CS1#≤0.2V,
=0mA,
=0mA,
to V
IL
IH
or OE#=V
CC
, V
IO
=V
SS
IH
to V
or
CC
Min
2.4
-1
-1
—
Min Typ Max Unit
Min Typ Max Unit
Min Typ Max Unit
—
—
—
—
—
—
—
—
—
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
Max
0.4
—
100
TBD
TBD
120
1
1
30
35
80
35
40
45
7
7
Unit
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
µA
V
V
81