S71PL512ND0JAW5B0 SPANSION [SPANSION], S71PL512ND0JAW5B0 Datasheet - Page 88

• Manufacturer Part Number: S71PL512ND0JAW5B0
• Description: Two S29PL256N Devices (32 M x 16-Bit) CMOS 3.0-Volt only Simultaneous Read/Write, Page-Mode Flash Memory
• Manufacturer: SPANSION [SPANSION]

86
Notes:
1.
2.
3.
4.
Data out
CS 1#
CS 2
Address
UB#, LB#
WE#
Address
Data in
CS1#
CS2
UB#, LB#
WE#
Data in
Data out
A write occurs during the overlap (t
low with asserting UB# or LB# for single byte operation or simultaneously asserting UB# and LB# for double byte
operation. A write ends at the earliest transition when CS1# goes high and WE# goes high. The t
the beginning of write to the end of write.
t
t
t
going high.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the CS1# going low to the end of write.
is measured from the end of write to the address change. t
Figure 27.7. Timing Waveform of Write Cycle(4) (UB#, LB# Controlled)
Figure 27.6. Timing Waveform of Write Cycle(3) (CS2 Controlled)
WP
) of low CS1# and low WE#. A write begins when CS1# goes low and WE# goes
t
AS
pSRAM Type 2
t
AS
P r e l i m i n a r y
High-Z
High-Z
t
t
t
AW
t
AW
CW
CW
t
t
WC
t
WP
t
WC
BW
t
WP(1)
t
WR
BW
is applied in case a write ends with CS1# or WE#
t
DW
Data Valid
t
DW
Data Valid
t
WR
t
t
WR
DH
t
DH
pSRAM_15_A2 February 3, 2005
WP
is measured from