9DB1233AGLF IDT [Integrated Device Technology], 9DB1233AGLF Datasheet

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Twelve Output Differential Buffer for PCIe Gen3 Recommended Application 12 output PCIe Gen3 zero-delay/fanout buffer General Description The 9DB1233 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1233 is driven by a ...

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Twelve Output Differential Buffer for PCIe Gen3 Pin Configuration SMBus Address Selection (Pin 29) ADR_SEL Voltage SMBus Adr (Wr/Rd) Low <0.8V Mid 1.2<Vin<1.8V High Vin > 2.0V ® IDT Twelve Output Differential Buffer for PCIe Gen3 VDD 1 64 ...

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Twelve Output Differential Buffer for PCIe Gen3 Pin Description PIN # PIN NAME 1 VDD 2 DIF_IN 3 DIF_IN# 4 GND 5 OE0# 6 DIF_0 7 DIF_0# 8 VDD 9 GND 10 OE1# 11 DIF_1 12 DIF_1# 13 OE2# ...

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Twelve Output Differential Buffer for PCIe Gen3 Pin Description (cont.) PIN # PIN NAME 33 SMBDAT 34 GND 35 BYPASS#/PLL 36 VTTPWRGD#/PD 37 DIF_6# 38 DIF_6 39 OE6# 40 GND 41 VDD 42 DIF_7# 43 DIF_7 44 OE7# 45 ...

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Twelve Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage VDDA 3.3V Logic Supply Voltage VDD Input Low Voltage V IL Input High Voltage V IH Input High Voltage V ...

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Twelve Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Clock Input Parameters Supply Voltage VDD = 3.3 V +/-5% COM; PARAMETER SYMBOL Input High Voltage - DIF_IN V IHDIF Input Low Voltage - DIF_IN V ...

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Twelve Output Differential Buffer for PCIe Gen3 Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics Supply Voltage VDD = 3.3 V +/-5% COM; PARAMETER SYMBOL PLL Bandwidth BW PLL Jitter Peaking t JPEAK ...

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Twelve Output Differential Buffer for PCIe Gen3 Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window 1 Clock 1us Symbol Lg- -SSC Absolute Short-term Period Average Definition Minimum Minimum Absolute Absolute Period Period 9.87400 9.99900 DIF DIF 100 ...

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Twelve Output Differential Buffer for PCIe Gen3 Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device Differential Routing ...

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Twelve Output Differential Buffer for PCIe Gen3 Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = R1 R2a ...

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Twelve Output Differential Buffer for PCIe Gen3 General SMBus serial interface information for the 9DB1233 How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC • IDT clock will acknowledge • ...

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Twelve Output Differential Buffer for PCIe Gen3 SMBus Table: Frequency Select Register Byte 0 Pin # Name Bit 7 - HIGH_BW# Bit 6 - BYPASS#/PLL Bit 5 - Reserved - Reserved Bit 4 - Reserved Bit 3 Bit 2 ...

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Twelve Output Differential Buffer for PCIe Gen3 SMBus Table: Output Enable Readback Byte 4 Pin # Name Bit 7 - Reserved Bit 6 - Reserved - Reserved Bit 5 Bit 4 - Reserved 58,59 OE11# Bit 3 53,54 OE10# ...

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... Ordering Information Part / Order Number Shipping Packaging 9DB1233AGLF 9DB1233AGLFT Tape and Reel “LF” after the package code denotes the Pb-Free configuration, RoHS compliant. “A” is the device revision designator (will not correlate with the datasheet revision). ® IDT Twelve Output Differential Buffer for PCIe Gen3 ...

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Twelve Output Differential Buffer for PCIe Gen3 Revision History Rev. Issue Date Who Description 0.1 7/7/2010 RDW Initial Release 1. Changed 'PWD' to 'Default' in SMBus 2. Updated Electrical Tables A 7/12/2010 RDW 3. Move to Final 1. Corrected ...