9DB1233AGLF IDT [Integrated Device Technology], 9DB1233AGLF Datasheet - Page 3

• Manufacturer Part Number: 9DB1233AGLF
• Description: Twelve Output Differential Buffer for PCIe Gen3
• Manufacturer: IDT [Integrated Device Technology]

Pin Description
IDT
PIN #
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
®
1
2
3
4
5
6
7
8
9
Twelve Output Differential Buffer for PCIe Gen3
VDD
DIF_IN
DIF_IN#
GND
OE0#
DIF_0
DIF_0#
VDD
GND
OE1#
DIF_1
DIF_1#
OE2#
DIF_2
DIF_2#
GND
VDD
OE3#
DIF_3
DIF_3#
OE4#
DIF_4
DIF_4#
VDD
GND
OE5#
DIF_5
DIF_5#
**ADR_SEL
HIGH_BW#
VDD
SMBCLK
PIN NAME
TYPE
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
PWR
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Power supply, nominal 3.3V
0.7 V Differential TRUE input
0.7 V Differential Complementary Input
Ground pin.
Active low input for enabling DIF pair 0.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
Active low input for enabling DIF pair 5.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
This tri-level input selects one of 3 SMBus addresses. See the SMBus
Address Select Table for the addresses.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
Clock pin of SMBUS circuitry, 5V tolerant
3
DESCRIPTION
1675B—11/08/10