9DB1233AGLF IDT [Integrated Device Technology], 9DB1233AGLF Datasheet - Page 7

• Manufacturer Part Number: 9DB1233AGLF
• Description: Twelve Output Differential Buffer for PCIe Gen3
• Manufacturer: IDT [Integrated Device Technology]

IDT
TA = T
1
2
3
4
TA = T
1
2
3
4
5
6
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
Electrical Characteristics - PCIe Phase Jitter Parameters
Guaranteed by design and characterization, not 100% tested in production.
I
Applies to all outputs when driven by 932SQ420DGLF or equivalent.
See http://www.pcisig.com for complete specs
Measured from differential waveform
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
Subject to final radification by PCI SIG.
Calculated from Intel-supplied Clock Jitter Tool v 1.6.4
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter) = SQRT{(total jittter)^2 - (input jitter)^2}
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
REF
Skew, Output to Output
Phase Jitter, PLL Mode
®
Skew, Input to Output
Additive Phase Jitter,
Duty Cycle Distortion
Jitter, Cycle to cycle
Twelve Output Differential Buffer for PCIe Gen3
PLL Jitter Peaking
= V
PLL Bandwidth
COM;
PARAMETER
COM;
PARAMETER
Bypass Mode
Duty Cycle
DD
/(3xR
Supply Voltage VDD = 3.3 V +/-5%
Supply Voltage VDD = 3.3 V +/-5%
R
). For R
R
= 475
SYMBOL
SYMBOL
t
t
t
t
t
t
jphPCIeG1
jphPCIeG2
jphPCIeG3
jphPCIeG1
jphPCIeG2
jphPCIeG3
t
t
t
t
jcyc-cyc
JPEAK
pdBYP
t
pdPLL
BW
t
t
DCD
sk3
DC
(1%), I
Measured differentially, Bypass Mode @100MHz
REF
= 2.32mA. I
(PLL BW of 2-4MHz, CDR = 10MHz)
(PLL BW of 2-4MHz, CDR = 10MHz)
Measured differentially, PLL Mode
Additive Jitter in Bypass Mode
1.5MHz < f < Nyquist (50MHz)
1.5MHz < f < Nyquist (50MHz)
-3dB point in High BW Mode
-3dB point in Low BW Mode
Bypass Mode, V
PCIe Gen 2 High Band
PCIe Gen 2 High Band
Peak Pass band Gain
PLL Mode V
PCIe Gen 2 Lo Band
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
10kHz < f < 1.5MHz
OH
CONDITIONS
CONDITIONS
PCIe Gen 1
PCIe Gen 3
PCIe Gen 1
PCIe Gen 3
V
PLL mode
= 6 x I
T
= 50%
REF
T
= 50%
T
7
and V
= 50%
OH
= 0.7V @ Z
O
=50 .
2500
MIN
-250
MIN
0.7
45
-2
2
TYP
49.5
TYP
0.35
1.5
1.1
2.2
0.4
0.5
0.8
45
25
25
34
3
1
0
2
MAX
MAX
4500
250
1.4
3.1
0.6
0.5
55
50
50
50
86
4
2
2
3
5
1
1
ps (p-p)
ps (p-p)
1675B—11/08/10
UNITS NOTES
UNITS
(rms)
(rms)
(rms)
(rms)
(rms)
(rms)
MHz
MHz
dB
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
1,2,4,5,
1,2,4,5
Notes
1,2,3
1,2,3
1,2,6
1,2,6
1,4
1,3
1,3
1,2
1,2
1
1
1
1
1
1
1
6