9DB1904BKLF IDT [Integrated Device Technology], 9DB1904BKLF Datasheet

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9DB1904BKLF

Manufacturer Part Number
9DB1904BKLF
Description
19 Output Differential Buffer for PCIe Gen2 and QPI
Manufacturer
IDT [Integrated Device Technology]
Datasheet
19 Output Differential Buffer for PCIe Gen2 and QPI
Description
The 9DB1904 is electrically compatible to the Intel DB1900GS
Differential Buffer Specification. This buffer provides 19 output clocks
for PCI-Express Gen2 or Intel QPI 6.4GT/s applications. A differential
clock from a CK410B+ main clock generator, such as the
ICS932S421 drives the 9DB1904. The 9DB1904 can provide
outputs up to 400MHz in Bypass Mode.
Recommended Application
19 Output Differential Buffer for PCIe Gen2 and QPI
Key Specifications
Pin Configuration
IDT
Functionality at Power Up (PLL Mode)
100M_133M#
®
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 150ps across all outputs
19 Output Differential Buffer for PCIe Gen2 and QPI
1
0
CLK_IN
100MHz
133MHz
100M_133M#_LV
MHz
OE_01234# 18
HIGH_BW# 4
DIF_0# 7
DIF_1# 9
DIF_2# 13
DIF_3# 15
DIF_4# 17
VDDA
GNDA
DIF_0 6
DIF_1 8
DIF_2 12
DIF_3 14
DIF_4 16
IREF
GND 10
VDD 11
1
2
3
5
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
DIF_(18:0)
CLK_IN
CLK_IN
MHz
9DB1904BKLF
1
Features/Benefits
Power Down Functionality
CKPWRGD_
PD#
Power up default is all outputs in 1:1 mode/No SMBus
programming
Spread spectrum compatible/EMI reductions
Supports output frequencies up to 400 MHz in bypass
mode/flexible fanout buffer
8 Selectable SMBus addresses/no SMBus
segmentation required
SMBus address determines PLL or Bypass mode/pin
savings
Dedicated VDDA and CKPWRGD_PD# pins/easy board
design
1
0
INPUTS
CLK_IN#
CLK_IN/
Running
X
54 OE14#
53 DIF_13#
52 DIF_13
51 OE13#
50 DIF_12#
49 DIF_12
48 OE12#
47 VDD
46 GND
45 DIF_11#
44 DIF_11
43 OE11#
42 DIF_10#
41 DIF_10
40 OE10#
39 DIF_9#
38 DIF_9
37 OE9#
OUTPUTS
DIF/DIF#
Running
Hi-Z
9DB1904B
Datasheet
1607C
—04/19/11
PLL State
OFF
ON

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9DB1904BKLF Summary of contents

Page 1

... IREF 1 GNDA 2 VDDA 3 5 DIF_0 6 DIF_1 8 9DB1904BKLF GND 10 VDD 11 DIF_2 12 DIF_3 14 DIF_4 Power up default is all outputs in 1:1 mode/No SMBus programming Spread spectrum compatible/EMI reductions ...

Page 2

Output Differential Buffer for PCIe Gen2 and QPI Pin Description PIN # PIN NAME PIN TYPE 1 IREF 2 GNDA 3 VDDA 4 HIGH_BW# 5 100M_133M#_LV 6 DIF_0 7 DIF_0# 8 DIF_1 9 DIF_1# 10 GND 11 VDD ...

Page 3

Output Differential Buffer for PCIe Gen2 and QPI Pin Description (continued) PIN # PIN NAME PIN TYPE 37 OE9# 38 DIF_9 OUT 39 DIF_9# OUT 40 OE10# 41 DIF_10 OUT 42 DIF_10# OUT 43 OE11# 44 DIF_11 OUT ...

Page 4

Output Differential Buffer for PCIe Gen2 and QPI Functional Block Diagram OE(17_18)# 13 OE(15_16)# OE(14:5)#, OE_01234# CLK_IN CLK_IN# HIGH_BW# 100M_133M#_LV CKPWRGD_PD# SMB_A0 SMB_A1 SMB_A2_PLLBYP# SMBDAT SMBCLK Power Groups Pin Number VDD GND 3 2 11,27,47,63 10,28,46,64 9DB1904 Frequency ...

Page 5

Output Differential Buffer for PCIe Gen2 and QPI Electrical Characteristics - Absolute Maximum Ratings PARAMETER SYMBOL 3.3V Core Supply Voltage VDDA 3.3V Logic Supply Voltage VDD Input Low Voltage V IL Input High Voltage V IH Input High ...

Page 6

Output Differential Buffer for PCIe Gen2 and QPI Electrical Characteristics - Input/Supply/Common Parameters Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions COM; PARAMETER SYMBOL Ambient Operating T COM Temperature Input ...

Page 7

Output Differential Buffer for PCIe Gen2 and QPI Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions COM; PARAMETER SYMBOL Slew rate ...

Page 8

Output Differential Buffer for PCIe Gen2 and QPI Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics Supply Voltage VDD = 3.3 V +/-5% COM; PARAMETER SYMBOL PLL Bandwidth BW PLL Jitter Peaking ...

Page 9

Output Differential Buffer for PCIe Gen2 and QPI Electrical Characteristics - Phase Jitter Parameters Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions COM; PARAMETER SYMBOL t jphPCIeG1 t jphPCIeG2 Phase ...

Page 10

Output Differential Buffer for PCIe Gen2 and QPI Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace Rs Rt Down Device ...

Page 11

Output Differential Buffer for PCIe Gen2 and QPI Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 R1a = R1b = ...

Page 12

Output Differential Buffer for PCIe Gen2 and QPI SMB_A(2:0) = 000 SMB Adr: D0 9DB1904 SMB_A(2:0) = 001 SMB Adr: D2 9DB1904 SMB_A(2:0) = 010 SMB Adr: D4 9DB1904 SMB_A(2:0) = 011 SMB Adr: D6 9DB1904 SMB_A(2:0) = ...

Page 13

Output Differential Buffer for PCIe Gen2 and QPI General SMBus serial interface information for the 9DB1904B How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address D4 • IDT clock will ...

Page 14

Output Differential Buffer for PCIe Gen2 and QPI SMBusTable: Reserved Register Byte 0 Pin # Name Bit 7 - Bit Bit 5 Bit 4 - Bit 3 - Bit Bit 1 Bit ...

Page 15

Output Differential Buffer for PCIe Gen2 and QPI SMBusTable: Output Enable Readback Register Byte 4 Pin # Name 69 Readback - OE17_18# Input Bit 7 Bit 6 60 Readback - OE15_16# Input Bit 5 Bit 4 54 Readback ...

Page 16

Output Differential Buffer for PCIe Gen2 and QPI SMBusTable: Control Pin Readback Register Byte 8 Pin # Name 5 Readback -100M_133M#_LV Bit 7 Bit 6 Bit 5 DIF_18 Bit 4 Bit 3 DIF_17 DIF_16 Bit 2 Bit 1 ...

Page 17

... Ordering Information Part / Order Number Shipping Packaging 9DB1904BKLF 9DB1904BKLFT Tape and Reel "LF" suffix to the part number are the Pb-Free configuration, RoHS compliant. "B" is the device revision designator (will not correlate with the datasheet revision). 19 Output Differential Buffer for PCIe Gen2 and QPI ® ...

Page 18

Output Differential Buffer for PCIe Gen2 and QPI Revision History Rev. Issue Date Description 0.1 7/1/2009 Initial release 0.2 7/8/2009 Updated revision ID in Byte 5 Updated electrical characteristics tables. A 9/21/2010 Added Test loads and terminations Corrected ...

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