9DB1904BKLF IDT [Integrated Device Technology], 9DB1904BKLF Datasheet - Page 6

• Manufacturer Part Number: 9DB1904BKLF
• Description: 19 Output Differential Buffer for PCIe Gen2 and QPI
• Manufacturer: IDT [Integrated Device Technology]

IDT
TA = T
1
2
3
4
5
Electrical Characteristics - Input/Supply/Common Parameters
SMBus Output Low Voltage
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are >200 mV
DIF_IN input
The differential input clock must be running for the SMBus to be active
SMBus Input High Voltage
SMBus Input Low Voltage
SCLK/SDATA Rise Time
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
SCLK/SDATA Fall Time
®
Low Threshold Input-
Low Threshold Input-
Nominal Bus Voltage
SMBus Sink Current
Input SS Modulation
19 Output Differential Buffer for PCIe Gen2 and QPI
Ambient Operating
Input High Voltage
Input Low Voltage
SMBus Operating
Input Frequency
Clk Stabilization
Pin Inductance
COM;
PARAMETER
Input Current
OE# Latency
High Voltage
Temperature
Low Voltage
Capacitance
Tdrive_PD#
Frequency
Frequency
Trise
Supply Voltage VDD/VDDA = 3.3 V +/-5%, See Test Loads for Loading Conditions
Tfall
SYMBOL
C
f
t
V
V
V
I
V
t
V
V
f
MAXSMB
T
LATOE#
INDIF_IN
PULLUP
t
T
C
DRVPD
t
F
MODIN
OLSMB
DDSMB
RSMB
V
I
F
F
L
C
IHSMB
FSMB
V
IH_FS
ILSMB
IL_FS
STAB
I
COM
INP
t
ibyp
OUT
t
IN
pin
ipll
ipll
R
IH
IN
F
IL
V
stabilization or de-assertion of PD# to 1st clock
IN
V
3.3 V +/-5%, Applies to 100M_133M#_LV pin
3.3 V +/-5%, Applies to 100M_133M#_LV pin
Single-ended inputs, V
IN
= VDD; Inputs with internal pull-down resistors
From V
Single-ended inputs, except SMBus, low
Single-ended inputs, except SMBus, low
= 0 V; Inputs with internal pull-up resistors
Maximum SMBus operating frequency
V
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
V
DD
DIF stop after OE# deassertion
DIF_IN differential clock inputs
DD
DIF start after OE# assertion
threshold and tri-level inputs
threshold and tri-level inputs
Logic Inputs, except DIF_IN
= 3.3 V, 133.33MHz PLL mode
V
Rise time of control inputs
DD
Fall time of control inputs
= 3.3 V, 100MHz PLL mode
DD
Output pin capacitance
(Triangular Modulation)
DIF output enable after
Allowable Frequency
Power-Up and after input clock
Commmercial range
Single-ended inputs
= 3.3 V, Bypass mode
3V to 5V +/- 10%
PD# de-assertion
CONDITIONS
@ I
@ V
PULLUP
IN
OL
6
= GND, V
IN
= VDD
GND - 0.3
V
SS
MIN
-200
120
0.7
1.5
1.5
2.1
2.7
33
90
30
-5
0
2
4
4
- 0.3
100.00
133.33
TYP
V
V
V
DD
DD
MAX
1000
0.35
200
400
110
147
300
DDSMB
300
100
0.8
2.7
1.8
0.8
0.4
5.5
70
33
12
5
7
5
6
5
5
+ 0.3
+ 0.3
1607C—04/19/11
UNITS NOTES
clocks
MHz
MHz
MHz
kHz
kHz
ms
mA
uA
uA
nH
pF
pF
pF
us
ns
ns
°C
ns
ns
V
V
V
V
V
V
V
V
1,4
1,2
1,3
1,3
1,2
1,2
1,5
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
1