9DB1904BKLF IDT [Integrated Device Technology], 9DB1904BKLF Datasheet - Page 3

• Manufacturer Part Number: 9DB1904BKLF
• Description: 19 Output Differential Buffer for PCIe Gen2 and QPI
• Manufacturer: IDT [Integrated Device Technology]

Pin Description (continued)
IDT
PIN #
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
®
19 Output Differential Buffer for PCIe Gen2 and QPI
OE9#
DIF_9
DIF_9#
OE10#
DIF_10
DIF_10#
OE11#
DIF_11
DIF_11#
GND
VDD
OE12#
DIF_12
DIF_12#
OE13#
DIF_13
DIF_13#
OE14#
DIF_14
DIF_14#
CKPWRGD_PD#
DIF_15
DIF_15#
OE15_16#
DIF_ 16
DIF_16#
VDD
GND
DIF_17
DIF_17#
DIF_18
DIF_18#
OE17_18#
CLK_IN
CLK_IN#
SMB_A2_PLLBYP#
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Active low input for enabling DIF pair 9.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 10.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 11.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 13.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 14.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 15 and 16.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pairs 17 and 18.
1 =disable outputs, 0 = enable outputs
True Input for differential reference clock.
Complementary Input for differential reference clock.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
3
DESCRIPTION
1607C—04/19/11