9DB1904BKLF IDT [Integrated Device Technology], 9DB1904BKLF Datasheet - Page 8

• Manufacturer Part Number: 9DB1904BKLF
• Description: 19 Output Differential Buffer for PCIe Gen2 and QPI
• Manufacturer: IDT [Integrated Device Technology]

IDT
TA = T
1
2
3
4
5
6
7
8
9
10
be set to high bandwidth. Differential phase jitter is the accumulation of the phase jitter not shared by the outputs (eg. not including
the affects of spread spectrum). Target ranges of consideration are agents with BW of 1-22MHz and 11-33MHz.
11
12
parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock in Spread Spectrum mode.
The 9DB1904's must be set to high bandwidth. The spread spectrum characteristics are: maximum of 0.5%, 30-33KHz modulation
frequency, linear profile.
13
Electrical Characteristics - Output Duty Cycle, Jitter, Skew and PLL Characterisitics
Guaranteed by design and characterization, not 100% tested in production. C
Measured from differential cross-point to differential cross-point
VT = 50% of Vout
PLL mode Input-to-Output skew is measured at the first output edge following the corresponding input.
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
This parameter is deterministic for a given device
Measured with scope averaging on to find mean value.
Long-term variation from nominal of input-to-output skew over temperature and voltage for a single device.
9DB1904B
19 Output Differential Buffer for PCIe Gen2 and QPI
This parameter is measured at the outputs of two separate 9DB1904 devices driven by a single main clock. The 9DB1904's must
This parameter is an absolute value. It is not a double-sided figure.
t is the period of the input clock
Differential spread spectrum tracking error is the difference in spread spectrum tracking between two 9DB1904 devices This
Skew, Output to Output
®
Skew, Input to Output
Duty Cycle Distortion
Jitter, Cycle to cycle
19 Output Differential Buffer for PCIe Gen2 and QPI
PLL Jitter Peaking
DIF_IN, DIF [x:0]
DIF_IN, DIF [x:0]
PLL Bandwidth
COM;
PARAMETER
Duty Cycle
DIF[X:0]
DIF[X:0]
Supply Voltage VDD = 3.3 V +/-5%
SYMBOL
t
Δ t
Δ t
SSTERROR
t
t
t
t
jcyc-cyc
JPEAK
pdBYP
t
pdPLL
BW
pd_BYP
t
pd_PLL
t
t
DCD
JPH
sk3
DC
Input-to-Output Skew Variation in Bypass
mode
(over specified voltage / temperature operating
ranges)
Input-to-Output Skew Variation in PLL mode
(over specified voltage / temperature operating
ranges)
Differential Phase Jitter (RMS Value)
Differential Spread Spectrum Tracking Error
(peak to peak)
Bypass Mode, nominal value @ 25°C, 3.3V,
PLL Mode, nominal value @ 25°C, 3.3V,
Measured differentially, Bypass Mode
Measured differentially, PLL Mode
Additive Jitter in Bypass Mode
-3dB point in High BW Mode
-3dB point in Low BW Mode
Peak Pass band Gain
CONDITIONS
@100MHz
V
V
PLL mode
V
T
T
T
= 50%
= 50%
= 50%
8
LOAD
= 2pF
2500
MIN
100
0.7
45
-2
2
3700
|500|
|250|
TYP
49.5
300
100
1.4
40
40
25
3
1
1
2
MAX
4500
|600|
|350|
500
150
1.4
55
10
80
50
50
4
2
2
UNITS
MHz
MHz
1607C—04/19/11
dB
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
%
1,2,4,6,7,
1,2,3,6,7,
NOTES
8,9,13
8,9,13
1,7,10
1,7,12
1,2,5
1,2,4
1,2,3
1,2
1,2
1,2
1
1
1
1