IDT72V70200PFG8 IDT, Integrated Device Technology Inc, IDT72V70200PFG8 Datasheet - Page 13

• Manufacturer Part Number: IDT72V70200PFG8
• Description: IC DGTL SW 512X512 3.3V 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70200PFG8

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V70200PFG8

NOTE:
1. If bit 13 (PC) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (SAB0, bits 6-5, CAB4 - CAB0) are output on the
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
10-8,7
4-0
6,5
Bit
15
14
13
12
11
output channel and stream associated with this location.
LPBK
15
(1)
(1)
(1)
LPBK
(Per Channel Loopback)
V/C
(Variable/Constant
Throughput Delay)
PC
(Processor Channel)
CCO
(Control Channel Output)
OE
(Output Enable)
SAB3-0
(Source Stream Address Bits)
Unused
CAB4-0
(Source Channel Address Bits)
V/C
14
PC
13
Name
CCO
12
12
OE
11
When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback
operations, set the delay offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.
This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a
per-channel basis.
When 1, the contents of the connection memory are output on the corresponding output channel and stream.
Only the lower byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection
memory are the data memory address of the switched input channel and stream.
This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions
Must be zero for normal operation.
normally. When 0, the output driver is in a high-impedance state.
This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.
The binary value is the number of the data stream for the source of the connection.
The binary value is the number of the channel for the source of the connection.
SAB3
10
SAB2
9
SAB1
8
SAB0
7
13
6
0
Description
5
0
CAB4
4
CAB3
COMMERCIAL TEMPERATURE RANGE
3
CAB2
2
CAB1
1
CAB0
0