IDT72V70200PFG8 IDT, Integrated Device Technology Inc, IDT72V70200PFG8 Datasheet - Page 9

• Manufacturer Part Number: IDT72V70200PFG8
• Description: IC DGTL SW 512X512 3.3V 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70200PFG8

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V70200PFG8

IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
15-10
15-6
Read/Write Address:
Reset Value:
Bit
3-0
Read/Write Address:
Reset Value:
Bit
9-5
1-0
15
15
0
5
4
0
4
3
2
Unused
BPD4-0
(Block Programming Data)
BPE
(Begin Block Programming
OSB
(Output Stand By)
SFE
(Start Frame Evaluation)
Unused
14
14
Enable)
Unused
MBP
(Memory Block Program)
MS
(Memory Select)
STA3-0
(Stream Address Bits)
0
0
Name
13
13
0
0
Name
00
0000
01
0000
12
12
12
0
0
H
H
,
,
H
H
.
.
11
11
0
0
When 1, the connection memory block programming feature is ready for the programming of Connection
Memory high bits, bit 11 to bit 15. When 0, this feature is disabled.
When 0, connection memory is selected for read or write operations. When 1, the data memory is selected
(No microprocessor write operation is allowed for the data memory.)
The binary value expressed by these bits refers to the input or output data stream, which corresponds
Must be zero for normal operation.
for read operations and connection memory is selected for write operations.
to the subsection of memory made accessible for subsequent operations. (STA3 = MSB, STA0 = LSB)
HIGH, the device requires two frames to complete the block programming. After the programming function
Must be zero for normal operation.
These bits carry the value to be loaded into the connection memory block whenever the memory block
set to 1, the contents of the bits BPD4-0 are loaded into bit 15 to 11 of the connection memory. Bit 10 to
bit 0 of the connection memory are set to 0.
A zero to one transition of this bit enables the memory block programming function. The BPE and
has finished, the BPE bit returns to zero to indicate the operation is completed. When the BPE = 1, the BPE
or MBP can be set to 0 to ensure proper operation. When BPE = 1, the other bit in the IMS register
must not be changed for two frames to ensure proper operation.
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX15 are in high impedance mode. When
ODE= 0 and OSB = 1, the output driver of TX0 to TX15 function normally. When ODE = 1, TX0 to TX15
output drivers function normally.
A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR
cycle, set this bit to zero for at least one frame.
Must be zero for normal operation.
programming feature is activated. After the MBP bit in the control register is set to 1 and the BPE bit is
BPD4-0 bits in the IMS register have to be defined in the same write operation. Once the BPE bit is set
register changes from zero to one, the evaluation procedure stops. To start another fame evaluation
10
10
0
0
BPD4 BPD3 BPD2 BPD1 BPD0
9
0
9
8
0
8
7
0
7
9
6
0
6
Description
Description
MBP
5
5
BPE
MS
4
4
STA3 STA2 STA1 STA0
OSB
COMMERCIAL TEMPERATURE RANGE
3
3
SFE
2
2
1
1
0
0
0
0