IDT72V70200PFG8 IDT, Integrated Device Technology Inc, IDT72V70200PFG8 Datasheet - Page 8

• Manufacturer Part Number: IDT72V70200PFG8
• Description: IC DGTL SW 512X512 3.3V 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70200PFG8

• Circuit: 1 x 16:16
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 72V70200PFG8

NOTE:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
IDT72V70200 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 512 x 5
Input Rate
2.048 Mb/s 32 – (n-m) time-slots m-n + 32 time-slots m-n time-slots
A7
0
0
0
0
0
0
0
1
1
1
1
1
OE bit in Connection
(1)
Memory
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
m < n
A5
0
0
0
0
0
0
0
0
0
0
0
0
Delay for Variable Throughput Delay Mode
(m – output channel number)
(n – input channel number)
12
A4
0
0
0
0
0
0
0
0
0
1
1
.
m = n, n+1, n+2
A3
0
0
0
0
0
0
0
0
0
1
1
.
Don’t Care
ODE pin
0
0
1
1
A2
0
0
0
0
1
1
1
0
0
1
1
.
m > n+2
A1
0
0
1
1
0
0
1
0
0
1
1
.
OSB bit in IMS
A0
0
1
0
1
0
1
0
0
1
0
1
.
8
Don’t Care
Register
Input Rate
2.048 Mb/s
0
1
1
0
Interface Mode Selection Register, IMS
Frame Input Offset Register 0, FOR0
Frame Input Offset Register 1, FOR1
Frame Input Offset Register 2, FOR2
Frame Input Offset Register 3, FOR3
Frame Alignment Register, FAR
Delay for Constant Throughput Delay Mode
Control Register, CR
Location
COMMERCIAL TEMPERATURE RANGE
Ch30
Ch31
(m – output channel number)
Ch0
Ch1
(n – input channel number)
.
32 + (32 – n) + m time-slots
TX Output Driver
High-Impedance
High-Impedance
Per Channel
Status
Enable
Enable
Enable