IDT72V70840DA IDT, Integrated Device Technology Inc, IDT72V70840DA Datasheet - Page 5

• Manufacturer Part Number: IDT72V70840DA
• Description: IC DGTL SW 4096X4096 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70840DA

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V70840DA

LOOPBACK CONTROL
the TX output data to be looped backed internally to the RX input for diagnostic
purposes.
looped back to the RX input channel (i.e., data from TXn channel m routes to
the RXn channel m internally); if the LPBK bit is low, the loopback feature is
disabled. For proper per-channel loopback operation, the contents of frame
delay offset registers must be set to zero.
streams results in a throughput delay. The device can be programmed to
perform time-slot interchange functions with different throughput delay capabili-
ties on a per-channel basis. For voice applications, variable throughput delay
is best as it ensure minimum delay between input and output data. In wideband
data applications, constant throughput delay is best as the frame integrity of the
information is maintained through the switch.
delay selected in the V/C bit of the connection memory.
VARIABLE DELAY MODE (V/C BIT = 0)
destination channels and is independent of input and output streams. The
minimum delay achievable in the IDT72V70840 is three time-slots. If the input
channel data is switched to the same output channel (channel n, frame p), it will
be output in the following frame (channel n, frame p+1). The same is true if the
input channel n is switched to output channel n+1 or n+2. If the input channel
n is switched to output channel n+3, n+4,..., the new output data will appear in
the same frame. Table 2 shows the possible delays for the IDT72V70840 in the
variable delay mode.
CONSTANT DELAY MODE (V/C BIT = 1)
making use of a multiple data memory buffer. Input channel data is written into
the data memory buffers during frame n will be read out during frame n+2. In
the IDT72V70840, the minimum throughput delay achievable in the constant
delay mode will be one frame. For example, when input time-slot 31 is switched
to output time-slot 0. The maximum delay of 94 time-slots of delay occurs when
time-slot 0 in a frame is switched to time-slot 31 in the frame.
interface to improve integration into a system. With a 12-bit address bus and
a 16-bit data bus, read and writes are mapped directly into Data and Connection
memories and require only one cycle to access. By allowing the internal
memories to be randomly accessed in one cycle, the controlling microprocessor
has more time to manage other peripheral devices and can more easily and
quickly gather information and setup the switch paths.
and Table 5 shows the Control Register information.
IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
The loopback control (LPBK) bit of each connection memory location allows
If the LPBK bit is high, the associated TX output channel data is internally
The switching of information from the input serial streams to the output serial
The delay through the device varies according to the type of throughput
In this mode, the delay is dependent only on the combination of source and
In this mode, frame integrity is maintained in all switching configurations by
The IDT72V70840’s microprocessor interface looks like a standard RAM
Table 4 shows the mapping of the addresses into internal memory blocks
5
MEMORY MAPPING
registers and memories of the IDT72V70840.
Memory, and Connection Memory. If A13 and A12 are HIGH, A11-A0 are used
to address the Data Memory. If A13 is HIGH and A12 is LOW, A11-A0 are used
to address Connection Memory. If A13 is LOW and A12 is HIGH A11-A0 are
used to select the Control Register, Frame Alignment Register, and Frame Offset
Registers. See Table 4 for mappings.
tions sections, after system power-up, the Control Register should be pro-
grammed immediately to establish the desired switching configuration.
bit (MBP), the Block Programming Data (BPE) bits, the Begin Block Program-
ming Enable (BPE), the Output Stand By, Start Frame Evaluation, and Data Rate
Select bits. As explained in the Memory Block Programming section, the BPE
begins the programming if the MBP bit is enabled. This allows the entire
connection memory block to be programmed with the Block Programming Data
bits. If the ODE pin is low, the OSB bit enables (if high) or disables (if low) all
TX output drivers. If the ODE pin is high, the contents of the OSB bit is ignored
and all TX output drivers are enabled.
CONNECTION MEMORY CONTROL
location controls the output drivers-enables (if high) or disables (if low). See
Table 3 for detail.
Processor Mode and Connection Mode. If high, the contents of the Connection
Memory are output on the TX streams. If low, the Stream Address Bit (SAB)
and the Channel Address Bit (CAB) of the Connection Memory defines the
source information (stream and channel) of the time-slot that will be switched to
the output from Data Memory.
Each Connection Memory location allows the per-channel selection between
variable and constant throughput delay modes.
looped back to the RX input channel (i.e., RXn channel m data comes from the
TXn channel m). If the LPBK bit is low, the loopback feature is disabled. For
proper per-channel loopback operation, the contents of the frame delay offset
registers must be set to zero.
the outputs should be put in high impedance by holding the ODE low. While the
ODE is low, the microprocessor can initialize the device, program the active
paths, and disable unused outputs by programming the OE bit in connection
memory. Once the device is configured, the ODE pin (or OSB bit depending
on initialization) can be switched.
The address bus on the microprocessor interface selects the internal
The two most significant bits of the address select between the registers, Data
As explained in the Serial Data Interface Timing and Switching Configura-
The data in the Control Register consists of the Memory Block Programming
If the ODE pin or the OSB bit is high, the OE bit of each connection memory
The Processor Channel (PC) bit of the Connection Memory selects between
Also in the Connection Memory is the V/C (Variable/Constant Delay) bit.
If the LPBK bit is high, the associated TX output channel data is internally
After power up, the state of the connection memory is unknown. As such,
COMMERCIAL TEMPERATURE RANGE