IDT72V70840DA IDT, Integrated Device Technology Inc, IDT72V70840DA Datasheet - Page 8

• Manufacturer Part Number: IDT72V70840DA
• Description: IC DGTL SW 4096X4096 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70840DA

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V70840DA

IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
15-13
10-0
Bit
12
11
Reset Value:
ST-BUS Frame
15
0
Name
Unused
CFE (Complete
Frame Evaluation)
FD11
(Frame Delay Bit 11) (FD11 = 0). This bit allows the measurement resolution to ½ CLK cycle.
FD10-0
(Frame Delay Bits)
Offset Value
Offset Value
GCI Frame
14
0
FE Input
FE Input
CLK
CLK
13
0
CFE
0000
Description
Must be zero for normal operation
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment offset. This bit is reset to
zero, when SFE bit in the CR register is changed from 1 to 0.
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1) or during the CLK-low phase
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to zero when the SFE bit of the
CR register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
12
H
.
FD11
11
0
0
1
1
FD10
Figure 1. Example for Frame Alignment Measurement
10
2
2
FD9
9
3
3
FD8
8
4
4
5
5
FD7
7
8
(FD[10:0] = 06
(FD11 = 0, sample at CLK LOW phase)
6
6
FD6
6
7
7
FD5
5
8
8
H
)
(FD[10:0] = 09
(FD11 = 1, sample at CLK HIGH phase)
FD4
9
9
4
10
10
FD3
3
COMMERCIAL TEMPERATURE RANGE
H
11
)
11
FD2
12
2
12
13
13
FD1
1
14
14
FD0
0
5715 drw 04
15
15
16