IDT72V70840DA IDT, Integrated Device Technology Inc, IDT72V70840DA Datasheet - Page 7

• Manufacturer Part Number: IDT72V70840DA
• Description: IC DGTL SW 4096X4096 144-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V70840DA

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-TQFP, 144-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V70840DA

IDT72V70840 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 4,096 x 4,096
11-7
Bit
6-0
15
14
13
12
15-10
LPBK
Bit
8-5
1-0
Reset Value:
9
4
3
2
15
15
0
Name
LPBK
(Per Channel Loopback)
V/C (Variable/Constant
Throughput Delay)
P C
(Processor Channel)
OE
(Output Enable)
SAB4-0 (Source Stream
Address Bits)
CAB6-0 (Source Channel
Address Bits)
V/C
Name
Unused
MBP
(Memory Block Program)
BPD3-0
(Block Programming Data)
BPE
(Begin Block
OSB
(Output Stand By)
SFE
(Start Frame Evaluation)
DR1-0
(Data Rate Select)
Programming Enable)
14
14
0
PC
13
13
0
0000
OE
12
12
0
H
.
Description
When 1, the RX n channel m data comes from the TX n channel m. For proper per channel loopback operations, set the delay
When 1, the contents of the connection memory are output on the corresponding output channel and stream. Only the lower
address of the switched input channel and stream.
This bit enables the TX output drivers on a per-channel basis. When 1, the output driver functions normally. When 0, the output
driver is in a high-impedance state.
The binary value is the number of the data stream for the source of the connection.
The binary value is the number of the channel for the source of the connection.
This bit is used to select between the variable (LOW) and constant delay (HIGH) mode on a per-channel basis.
offset register bits OFn[2:0] to zero for the streams which are in the loopback mode.
byte (bit 7 – bit 0) will be output to the TX output pins. When 0, the contents of the connection memory are the data memory
SAB4
11
11
0
Description
Must be zero for normal operation.
When 1, the connection memory block programming feature is ready for the programming of Connection Memory high bits,
bit 11 to bit 15. When 0, this feature is disabled.
loaded into bit 15 and 12 of the connection memory. Bit 11 to bit 0 of the connection memory are set to 0.
A zero to one transition of this bit enables the memory block programming function. The BPE and BPD4-0 bits in the CR
register have to be defined in the same write operation. Once the BPE bit is set HIGH, the device requires two frames to
operation is completed. When the BPE = 1, the BPE or MBP can be set to 0 to abort to ensure proper operation. When
BPE = 1, the other bit in the CR register must not be changed for two frames to ensure proper operation.
When ODE = 0 and OSB = 0, the output drivers of TX0 to TX31 are in high impedance mode. When ODE = 0 and OSB = 1,
the output driver of TX0 to TX31 function normally. When ODE = 1, TX0 to TX31 output drivers function normally.
A zero to one transition in this bit starts the frame evaluation procedure. When the CFE bit in the FAR register changes from
These bits carry the value to be loaded into the connection memory block whenever the memory block programming feature
complete the block programming. After the programming function has finished, the BPE bit returns to zero to indicate the
is activated. After the MBP bit in the control register is set to 1 and the BPE bit is set to 1, the contents of the bits BPD3-0 are
zero to one, the evaluation procedure stops. To start another fame evaluation cycle, set this bit to zero for at least one frame.
SAB3
10
DR1
10
0
0
0
1
1
SAB2
MBP
9
9
BPD3
SAB1
8
8
BPD2
SAB0
7
7
DR0
7
0
1
0
1
BPD1
CAB6
6
6
BPD0
CAB5
5
5
CAB4
BPE
2.048 Mb/s
4.096 Mb/s
8.192 Mb/s
Data Rate
Reserved
4
4
CAB3
OSB
COMMERCIAL TEMPERATURE RANGE
3
3
CAB2
SFE
2
2
CAB1
DR1
1
1
Master Clock
16.384 MHz
4.096 MHz
8.192 MHz
Reserved
CAB0
DR0
0
0